Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2000-08-09
2002-02-12
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S068000, C326S083000
Reexamination Certificate
active
06346829
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit design, and more particularly to, input buffer circuits on an integrated circuit.
BACKGROUND OF THE INVENTION
In the integrated circuit (IC) industry, input buffer circuitry is fabricated on a periphery of an integrated circuit die and electrically connected between an external pin of the integrated circuit and internal circuitry within the IC. In essence, the input buffer circuitry is an interface between the internal IC circuitry and an external environment outside of the IC so that data can be communicated from the external environment in to and out from the integrated circuit. Integrated circuits (ICs) are routinely designed such that one integrated circuit in an electrical system operates at a first power supply voltage and a second integrated circuit operates using a different power supply voltage level. For example, a first common voltage supply in the industry is roughly a 5 volt voltage supply, a second voltage supply used in the industry is roughly 3.3 volts, a third voltage commonly used in the industry is roughly 2.5 volts, and a fourth commonly used voltage supply level is roughly 1.8 volts where any electrical system may contain one or more devices operating at these voltage levels. As an example, for example, a 5 volt part will need to interface to a 1.8 volt part wherein the input buffer which is used to communicate between these two parts must be able to handle the discrepancy in voltage while still rendering acceptable performance. Due to the fact that there are at least four different common power supply voltage levels which are readily available in the industry, communication between these different devices has become more complex. Input and/or output buffer must now ensure interoperability of these different devices while maintaining optimal performance, if possible. Therefore, the design of such buffers has become increasingly more difficult and increasingly more important in the IC industry.
FIG. 1
illustrates a prior art input buffer
500
that is commonly used in the integrated circuit industry. The buffer of
FIG. 1
is fabricated on an IC die and allows two integrated circuits with different power supply voltages to interface to one another in a fairly efficient manner. The integrated circuit incorporating the circuit
500
contains a chip pad
512
in
FIG. 1
which is used to receive input data from external to the integrated circuit. An input signal provided to the chip pad/terminal
512
will pass through a resistive element
510
and be communicated through an input transistor
504
illustrated in FIG.
1
. The transistor
504
of
FIG. 1
has a gate/control electrode that is coupled to the outside VDD level (OVDD)
514
. The OVDD signal
514
is the power supply voltage level used by the external peripheral that is coupled to the pad
512
and providing the data into the circuit
500
. The OVDD signal
514
is provided into the integrated circuit via another pin coupled to the integrated circuit where the OVDD is not specifically illustrated in FIG.
1
. As a typical example, OVDD may be one of 5 volts, 3.3 volts, 2.5 volts, and 1.8 volts in most devices that use complementary metal oxide semiconductor (CMOS) silicon logic devices.
The transistor
504
ensures that the node
505
does not rise in voltage to a damaging voltage level that can harm the transistors
508
and
506
. Specifically, any voltage provided on the chip pad
512
through the resister
510
will drop at least a threshold voltage (Vt) in magnitude when communicated through the transistor
504
whereby the voltage on node
505
should be less than OVDD when OVDD
514
in
FIG. 1
is greater than VDD
516
. In short, transistor
504
will protect the transistors
508
and
506
from a damaging overvoltage occurrence that may occur when an integrated circuit operating at a first power voltage is coupled to another integrated circuit operating at a different second power supply voltage.
The input signal initially provided through the chip pad
512
is then provided via the node
505
to the inverter comprising transistors
506
and
508
. The inverter, comprising transistors
506
and
508
, is connected to a ground potential
520
and an internal VDD voltage
516
. The VDD voltage
516
is a voltage that is supplied to operate all the circuitry on the integrated circuit including the input buffer
500
. Typically, VDD
516
can be any voltage but is usually 2.5 volts or 1.8 volts in modern high performance low power microprocessors and memory. The inverter, comprising the transistors
506
and
508
, will buffer the input signal to an internal node
518
with a logical inversion. This inverted signal provided by transistors
506
and
508
is routed to functional located within the integrated circuit containing the circuit
500
so that incoming information may be processed by the system.
In case where OVDD
514
minus a threshold voltage (OVDD−Vt) is substantially less than VDD
516
in voltage, the transistor
502
is provided. Transistor
502
will pull the node
505
up to an acceptable voltage during certain conditions to shut off the inverter comprising transistors
506
and
508
when (OVDD−Vt) is substantially less than VDD. Therefore, transistor
502
ensures that, when a substantial mismatch of voltage occurs between OVDD and VDD, the inverter containing transistors
506
and
508
can be completely turned off regardless of this extreme difference in voltage.
While the circuit of
FIG. 1
is commonly used and is an adequate output buffer in most circumstances, the circuitry of
FIG. 1
has many disadvantages. First, due to the difference voltages OVDD
514
and VDD
516
, the inverter comprising transistors
506
and
508
is typically fixed to a trigger point that is directly a function of specific OVDD and VDD voltage values. For example, if OVDD is 5 volts and VDD is 3.3 volts, the trigger voltage of the inverter comprising gates
506
and
508
is statically fixed to roughly 2.5 volts, which is not half way between VDD and ground, when the devices
508
and
506
are matched. This is not advantageous since the inverter now has a trigger point that is not roughly half way between VDD
516
(3.3 volts) and ground
520
. To compensate for this noise margin problem, the transistors
508
and
506
are fabricated with significantly different in aspect ratios to statically fix the trigger point at yet another voltage value (e.g., 1.6 volts). This mismatching of the transistors
506
and
508
will result in an imbalanced and non-symmetrical inverter that will have different operating characteristics when the inverter is transitioning from a high voltage to a low voltage and vice versa. Since timing constraints of external buses and the like are typically designed to the worse case transition, the mismatch in the transistors
506
and
508
to correct noise margins may impact the maximal speed at which the device can be operated.
In addition, since the trigger point of
FIG. 1
is statically fixed, the circuitry of
FIG. 1
can only function optimally when OVDD
514
and VDD
516
are known quantities that will not change for different applications. If a designer wants to have flexibility to change VDD
516
to another voltage and/or to change OVDD
514
to another voltage, use the IC in a different application, or add different peripherals to the system having different OVDDs, then the statically designed circuit
500
of
FIG. 1
will not compensate for these changes in OVDD whereby the trigger point will not be properly set. Improperly set trigger points will greatly reduce the speed of operation of the circuit and may, in some circumstances, render the circuit of
FIG. 1
completely inoperable. For example, in the circuitry of
FIG. 1
, if (OVDD−Vt) were to be substantially less than VDD, the circuitry of
FIG. 1
may not even be able to pass a logic
1
from the chip pad
512
to the internal gates
518
. In this case, the circuitry of
FIG. 1
is completely nonfu
Motorola Inc.
Tokar Michael
Tran Anh
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