Electric power conversion systems – Current conversion – With voltage multiplication means
Reexamination Certificate
2002-02-15
2003-12-09
Vu, Bao Q. (Department: 2838)
Electric power conversion systems
Current conversion
With voltage multiplication means
C363S060000, C307S110000, C327S536000
Reexamination Certificate
active
06661682
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor circuitry. More particularly, the present invention relates to a charge pump circuit usable in a semiconductor.
2. Description of Related Art
High voltage generators using charge pump circuits have been widely used in various semiconductor products. These high voltage generators are used for generating programming or erasing voltage for non-volatile memory having floating gate devices, such as EPROM, EEPROM, or Flash EEPROM. The high voltage generator may also be used for RAM devices such as DRAM, SRAM, or FeRAM in order to boost word line voltage.
FIG.
1
(
a
) is the conventional charge pump circuit with four stages, disclosed in publication of IEEE Journal of Solid State Circuit, Vol. 11, pp. 374-378, June 1976, which is incorporated herein by reference in its entirety. Unit gain stage consists of NMOS switch(N
1
~N
4
) and pumping capacitor(C
1
~C
4
). The bulk of NMOSFETs are biased by constant voltage such as ground potential. Series connection of plurality of unit gain stage from node of supply voltage (Vdd) to output node forms the charge pump circuit. As shown in FIG.
1
(
b
), input pulses of the charge pump, CLK
1
and CLK
2
, should be non-overlapped pulses having the complementary phase. One drawback of the conventional circuit in FIG.
1
(
a
) is that the gain is limited by an increment of the threshold voltage due to body effects. The gain of a stage is about Vdd−Vtn, where Vdd is the supply voltage and Vtn is the threshold voltage of a NMOSFET in the nth stage. Since the bulk potential is biased by constant voltage, the reverse biased voltage between source and bulk(VBS) is increased according to charge up of source node. Since the threshold voltage of nMOSFET is increased with VBS due to the body effects, the threshold voltage of NMOSFET is increased according to an increment of the output voltage. If the Vdd is lower than Vtn, the gain is zero. This circuit needs a pre-charge transistor(N
0
) between the node of Vdd and the first stage of pump. The pre-charge transistor between Vdd and the first stage is also caused by additional threshold voltage drop.
To overcome the limitations of the conventional charge pump, a variety of modified circuits have been reported in the relevant art. The approach to overcome the voltage loss due to threshold voltage drop is by boosting the gate voltage of pass transistors by incorporating additional gate boosting capacitors and charge-up transistors. The conventional charge pump circuit having a unit stage, which consists of two NMOSFETs and two capacitors is disclosed in the IEEE Journal of Solid State Circuit, Vol. 27, pp. 1540-1545, November, 1992, which is incorporated herein by reference in its entirety. FIG.
2
(
a
) shows the conventional high voltage generator using two NMOS switches one for pass transistor (Np
1
~Np
4
) and the other for gate boosting transistor (NB
1
~Nb
4
) with gate boosting capacitor (CB
1
~CB
4
). The pump is controlled by four clock-pulses having two basic complementary phases with several non-overlapped timing margins.
FIG.
2
(
b
) shows the control clocks for the conventional circuit of FIG.
2
(
a
). The amplitude of the clocks is the same as the supply voltage (Vdd). CLK
2
and CLK
4
are inputs of gate capacitors, where the gate voltage boosted by these input-clocks controls the pass transistors to control whether these are ON or OFF. CLK
1
and CLK
3
are input pulses to pumping capacitors (CP
1
~CP
4
). In FIG.
2
(
b
), the following timing margins are critical for proper operation. The duration of Tp
2
and Tp
4
is the time for turning on the pass transistor for transferring charge to the next stage. The margin of T
14
r, T
14
f, T
23
r, and T
23
f is inhibiting timing margin of turning on the pass transistors to prevent reverse charge flow from output to input direction. T
13
is the timing margin for pre-charging gate boosting capacitors (CB
1
~CB
4
). The gate boosting capacitor is pre-charged when the gate voltage of the gate boosting transistor is high while the input clock of the gate boosting capacitor is low and the voltage of the input port is high (timing represented by T
13
in the FIG.
2
(
b
). When the input pulse of the gate boosting capacitor is high, the high level of the gate voltage becomes
Vpc+&agr;*Vdd (1)
where Vpc is a value of pre-charged voltage and &agr; is the coupling coefficient between the gate boosting capacitor and the parasitic capacitance of the gate node of pass transistors. The value of &agr; is obtained as:
&agr;=
CB/
(
CB+Cparag
), (2)
where CB is the capacitance of the gate boosting capacitor and Cparag is the parasitic capacitance of the gate node of the pass transistors. The voltage over-drive of the gate node of the pass transistor upon the pre-charged level is about “&agr;* Vdd.” The peak level of charge pumping capacitor is:
Vpc+&bgr;*Vdd. (3)
where &bgr; is the coupling coefficient between the charge pumping capacitor and the parasitic capacitance of the drain node of the pass transistors. The value of &bgr; is obtained as:
&bgr;=
CP/
(
CP+Cparad
), (4)
where CP is the capacitance of the charge pumping capacitor and Cparad is the parasitic capacitance of the drain node of the pass transistors. The gate voltage of the pass transistor during charge transfer is maintained at a level about &agr;Vdd is higher than its pre-charged level.
The unit gain of stage n is about Vdd−Vtn, so the gain restriction is the same as the conventional circuit shown in FIG.
1
(
a
), where Vtn is the threshold voltage of the pass transistor in the n
th
stage of the pump. This charge pump circuit can operate only when &agr;Vdd is larger than Vtn. The efficiency is improved compared to the conventional circuit in FIG.
1
(
a
), but the efficiency is still very low.
The drawbacks of the conventional charge pump circuit depicted in FIG.
2
(
a
) are as follows:
1) There is limitation of voltage gain due to body effects. Since NMOSFETs are biased by constant voltage, the threshold voltage is increased as the source voltage is increased.
2) The timing margins of T
14
f, T
14
r, T
23
r and T
23
f are required to prevent charge flow to reverse direction because the switch on the input side has to be in OFF state before the pumping pulse goes to the high state. The timing margin of T
13
and T
31
, overlapping margins between two pulses, are also necessary to pre-charge the gate boosting capacitors. Therefore, net time for charge transferring operation is limited. And it is very difficult to operate the pump in the high frequencies.
3) High voltage is applied on the gate electrodes of the pass transistors. According to the Equation (1), the maximum voltage across the gate oxide is about Vpc+&agr;*Vdd for transferring the voltage amount of “Vpc+&bgr;*Vdd−Vthn” to the capacitor of the next stage at the source side. As the MOS devices scaling down the dielectric thickness of gate oxide become thinner and thinner, the large voltage across the gate oxide may cause reliability problems such as dielectric breakdown, leakage current, and hot carrier effects, etc.
4) This charge pump circuit needs a termination switch between the end of the stage and the output node as represented by NP
0
in FIG.
2
(
a
). Since the output node has the highest potential among the circuits, the threshold voltage of this termination nNMOSFET is the most severe.
To overcome the threshold voltage drop due to the body effects of NMOS switches, a charge pump circuit with PMOSFETs on floating wells was disclosed in the U.S. Pat. No. 5,986,947, which is incorporated herein by reference in its entirety.
FIG. 3
shows the conventional charge pump circuit using PMOSFETs. Unit stage comprises one pumping capacitor (CP
1
~CP
4
) and one PMOS switch (MP
1
~MPN) on floating wells. The input pulses shown in FIG.
1
(
a
) can be used for this circuit. Since the wells are electrically floated, t
Kim Shi-Ho
Tsouhlarakis Jorgo
IMEC (Interuniversitair Microelectronica Centrum)
Jones Day
Vu Bao Q.
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