Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent
1998-03-09
2000-06-27
Santamauro, Jon
Electronic digital logic circuitry
Interface
Supply voltage level shifting
326 86, H03K 190185
Patent
active
060811323
ABSTRACT:
A high voltage drive output buffer for low voltage integrated circuits comprising a pullup pFET; a driver pFET having a source connected to the drain of the pullup pFET, and having a gate connected to a biasing circuit; a driver nFET having a drain connected to the drain of the driver pFET, and having a gate connected so as to be biased; and a pulldown nFET having a drain connected to the source of the driver nFET; wherein the pullup pFET and pulldown nFET are coupled to switch in complementary fashion in response to an input voltage; and wherein the biasing circuit comprises an nFET having a drain connected to the gate of the driver pFET and coupled to the input node so as to switch ON for a transitory period when the pullup pFET switches from OFF to ON.
REFERENCES:
patent: 5300832 (1994-04-01), Rogers
patent: 5440249 (1995-08-01), Schucker et al.
patent: 5506535 (1996-04-01), Ratner
patent: 5559464 (1996-09-01), Orii et al.
patent: 5834948 (1998-11-01), Yoshizaki et al.
Intel Corporation
Kalson Seth Z.
Santamauro Jon
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