Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-02
2002-01-15
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S339000, C257S347000, C257S370000, C257S378000, C257S401000, C257S507000, C257S514000, C438S202000, C438S219000, C438S234000, C438S694000
Reexamination Certificate
active
06339243
ABSTRACT:
This application claims the benefit of Korean Application No. 7178/1999 filed Mar. 4, 1999, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a high voltage device and a method for fabricating the same, in which a diode is used for reducing the influence of an electric field to silicon for enabling a higher operative voltage without an increased thickness of silicon on an upper portion thereof.
2. Background of the Related Art
In general, a power MOSFET has an excellent switching speed compared to other semiconductor devices. Also, because it has a comparatively low withstand voltage (below 300V), it has a low turn-on resistance. Accordingly, a high voltage lateral power MOSFET is frequently used as a power device for a high density device packing. Among high voltage power devices, there are, among others, DMOSFET (Double-diffused MOSFET), IGBT (Insulated Gate Bipolar Transistor), EDMOSFET (Extended Drain MOSFET) and LDMOSFET (Lateral Double-diffused MOSFET). Though the LDMOSFET has a variety of applications in chips, such as an HSD (High Side Driver), LSD (Low Side Driver) and an H-bridge circuit and can be fabricated easily, the LDMOSFET has disadvantages in that it has a high threshold voltage, and a breakdown can occur at the surface of a silicon substrate in a drift region near a channel because the doping concentration in the channel region of the LDMOSFET is not uniform.
A high voltage transistor developed recently to avoid the problems of earlier devices is an EDMOSFET. In general, because the maximum electric field intensity in a high voltage device, which increases as the operative voltage increases, limits operation characteristics of the device, the silicon should be thick. The thicker the silicon, the more difficult it is to provide dielectric isolation between devices. Presently, the technology for integrating high voltage devices and low voltage devices into one semiconductor chip is widely applied, according to which the technique of dielectric isolation between devices using an SOI (Silicon On Insulator) wafer is frequently used.
A related art high voltage device will be explained with reference to the attached drawings.
FIG. 1
illustrates a section of the related art high voltage device.
As shown in
FIG. 1
, the related art high voltage device is provided with a first conduction type substrate
11
, a buried oxide film
12
formed on the substrate
11
, and a first conduction type semiconductor layer
13
formed on the buried oxide film
12
. A second conduction type drift region
14
is formed in the semiconductor layer
13
, and a second conduction type well region
15
is formed in the second conduction type drift region
14
. A collector impurity region
16
is formed in the second conduction type well
15
region. A first conduction type drift region
17
is formed in the semiconductor layer
13
spaced from the second conduction type drift region
14
. A first conduction type well region
18
is formed in the first conduction type drift region
17
, an emitter impurity region
19
is formed in the first conduction type drift region
17
, and a first insulating layer
20
is formed on the second conduction type drift region and extends to one side of the emitter impurity region
19
. A second insulating layer
21
is formed on the first conduction type drift region
14
between the collector impurity region
16
and the second conduction type drift region
17
. A gate electrode
22
is formed on the first insulating layer
20
and extends to overlap a portion of the second insulating layer
21
. A third insulating layer
23
is formed on the second insulating layer
21
and the gate electrode
22
. An emitter electrode
19
a
, insulated from the gate electrode
22
by the third insulating layer
23
, is electrically connected to the emitter impurity region
19
. A collector electrode
16
a
is electrically connected to the collector impurity region
1
6
, and a field plate region
24
is formed to overlap with the gate electrode
22
with the third insulating layer
23
disposed therebetween. The field plate electrode
24
is formed to disperse an electric field formed in the second conduction type drift region
17
during operation to obtain a high breakdown voltage. Upon application of the operative voltage to the collector electrode
16
a
, the first conduction type drift region
14
is brought into a saturated depletion state to move electrons through the collector impurity region
16
.
While the related art high voltage device is operative as a power device, an equipotential is applied both to the gate electrode
22
and the field plate electrode
24
, so that the depletion region in the second conduction type drift region
17
disperses an electric field concentrated on an edge portion of the gate electrode
22
. This is done to prevent a breakdown occurrence at the edge portion of the gate electrode.
The thickness of the silicon layer having the high voltage device formed thereon in the aforementioned SOI wafer is determined according to a range of the high voltage, which can be expressed as follows.
V
=
(
t
s
2
+
3
t
ox
)
E
y
(
1
)
Where, V is the breakdown voltage, t
s
is the thickness of silicon, t
ox
is the thickness of the buried oxide film, and E
y
is a critical electric field of the silicon in a vertical direction.
FIG. 2
illustrates a voltage distribution of the related art high voltage device, wherefrom it can be understood that equipotential planes exist in the vertical direction as well as in a horizontal direction in an upper silicon layer. Furthermore, there are equipotential planes in a horizontal direction under the collector electrode, implying the presence of a vertical electric field therein.
FIG. 3
illustrates the electric field under the collector electrode in the related art device. It can be understood that there is an electric field, not in the horizontal direction, but in the vertical direction, and that there are horizontal equipotential planes under the collector electrode. The vertical electric field shows a maximum in the vicinity of a junction between a P-conduction type upper silicon layer and an N-conduction type drift region. This means that the depletion layer is formed and an electric field is centered on the junction when a voltage is started to be applied to the collector electrode. Therefore, though the depletion layer becomes wider and the electric field becomes larger as the voltage to the collector electrode becomes higher, the position of the maximum electric field shows no change.
FIG. 4
illustrates voltage vs. current of the collector when a voltage is applied to the gate electrode in the related art high voltage device. The measurements are obtained as a result of observation of the collector current as the collector voltage is increased after the application of a voltage to the gate electrode.
The related art high voltage device has the following problems. As can be known from equation (1), the higher the breakdown voltage, the thicker the silicon layer in the wafer must be. The thicker silicon layer requires a deeper trench for the dielectric isolation technique, which is not possible to form in an actual process. In order not to form the thicker silicon layer in the fabrication of the high voltage device, either the thickness of the oxide film must be increased or a critical electric field on the silicon layer must be made larger. However, increasing the thickness of the buried oxide film causes deflection of the wafer due to material properties of the oxide film and the silicon layer. T his causes poor fabrication of the device.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a high voltage device and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a high voltage device and a meth
Jin Jun Hee
Kwon Oh Kyong
Hyundai Electronics Industries Co,. Ltd.
Morgan Lewis & Bockius
Wojciechowicz Edward
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