High-Voltage CMOS transistors on a standard CMOS wafer

Details High-Voltage CMOS transistors on a standard CMOS wafer High-Voltage CMOS transistors on a standard CMOS wafer

1996-11-25

1998-08-04

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257371, 257375, 257376, 257408, H01L 2972

Patent

active

057897867

ABSTRACT:
A low-voltage 0.8-micron CMOS process is modified by implanting arsenic or phosphorus during epitaxy in a p-type substrate starting material to increase the depth of selected n-well areas for the purpose of producing high-voltage transistors on the same substrate in the same CMOS process. Implanting boron in a p-field extension area in a manner which minimizes the dopant in the adjacent field oxide achieves a similar result. That is, breakdown and punch-through voltages are increased. Together, these make CMOS transistors which operate at a higher voltage range than either innovation alone.

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Gilles, T. et al., "High-Voltage Technology Offers New Solutions for Interface Intergrated Circuits, "IEEE Transactions on Electron Devices, Vol. ED-33, No. 12, Dec. 1986, pp. 2016-2024.

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