High voltage CMOS switch

Details High voltage CMOS switch High voltage CMOS switch

2000-09-13

2002-04-09

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S230060, C326S081000, C327S055000

Reexamination Certificate

active

06370071

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits, more particularly to complementary metal oxide semiconductor integrated circuit switching devices, and more specifically to a ratio-less, high voltage, CMOS, switch for non-volatile memory, address data decoding, integrated circuit devices.
2. Description of Related Art
Complementary metal oxide silicon (“CMOS”) technology is a preferred fabrication process for many integrated circuit (“IC”) devices, particularly those in which low power consumption and high component density are priorities. Many publications describe the details of common techniques used in the fabrication of integrated circuits that can be generally employed in the fabrication of complex, three-dimensional, IC structures; see e.g.,
Silicon Processes
, Vol. 1-3, copyright 1995, Lattice Press, Lattice Semiconductor Corporation (assignee herein), Hillsboro, Oreg. Moreover, the individual steps of such a process can be performed using commercially available IC fabrication machines. The use of such machines and common fabrication step techniques will be referred to hereinafter as simply: “in a known manner.” The commonly used term “chip” is used to refer to an entire IC device. As specifically helpful to an understanding of the present invention, approximate technical data are disclosed herein based upon current technology; future developments in this art may call for appropriate adjustments as would be apparent to one skilled in the art.
In programmable non-volatile memory cells, such as row and column address decoder outputs, it is generally known to use a circuit that switches a relatively high voltage to the output based on a relatively low voltage input for an addressed cell. It will be recognized by those skilled in the art that such “switch” circuits (any electronic circuit that reverses and maintains a state, namely HIGH/LOW or 1/0, each time the input power changes) can have many other uses, such as signal level translators, output pad drivers, programming circuits, and the like.
FIG. 1
(Prior Art) is an electrical schematic of a typical IC, non-volatile memory, address decoder output, high voltage switching circuit
100
, “high V switch” for short. Four metal-oxide-silicon field effect transistors (“MOSFET”), N
1
, N
2
, P
1
(n-well device), P
2
(n-well device) and an inverter are used. [It will be recognized by those skilled in the art that all dopant types can be reversed]. The high V switch receives an input Enable signal, “En,” having a transition either from LOW-to-HIGH or HIGH-to-LOW (e.g., between a zero volt LOW and a two-and-a-half volt HIGH or other logic power supply voltage, “Vcc,” depending on the fabrication process design), and provides an output signal “OUT” that needs to be driven correspondingly (e.g., between a zero volt LOW and a thirteen volt HIGH or other generated fabrication process design level). The power supply to the circuit is a high voltage, “Vpp,” generated internally by other known manner circuitry of the IC (not shown), e.g., the desired output level, thirteen volts. In operation, when signal En is LOW, the inverter output, INV, is HIGH and transistor N
2
is ON, transistor P
1
is ON, transistors N
1
is OFF and P
2
are OFF (gate and source at Vpp), so OUTB is at Vpp and the signal OUT is switched to LOW. Note that N
1
and P
1
must be. designed in relative size to have a size ratio wherein N
1
is a much larger individual device than P
1
; similarly the size of N
2
>>P
2
. Thus, when signal En goes HIGH/Vcc, the inverter output goes LOW and N
2
is OFF, N
1
being ON overcomes P
1
, OUTB is pulled LOW, turning ON P
2
which feeds back into P
1
also trying to shut P
1
OFF, P
2
being ON is passing Vpp to switch the OUT signal node (and at the same time also turning OFF P
1
). In other words, to make the signal transition with this conventional circuit, the N
1
and N
2
devices have to overcome P
1
and P
2
devices so they must be much larger in design, using valuable IC chip space. Depending on the process and device parameters N
1
and N
2
may be as much as five times as large as P
1
and P
2
. Thus, this circuit is also relatively slow. Moreover, during this difficult transition, excessive power is used. Furthermore, the individual devices must be built to handle the high voltage without breakdowns (grounded gate (e.g, in
FIG. 1
when N
1
is OFF, having the gate at LOW and the source grounded, yet the OUT node is at Vpp at the start of an En LOW and INV transition to 1), n-well (e.g., in the p-type devices, the n-well is tied to Vpp), n+/p+ junction breakdowns), such as by having relatively very thick (>250 Angstroms) gate oxide to handle the high voltage levels, complicating fabrication process steps.
It is common to shorthand the system function via a logic table, such as Table 1, also provided for the remaining Figures discussed:
TABLE 1
En
INV
N1
P1
N2
P2
OUTB
OUT
LOW
1
OFF
ON
ON
OFF
Vpp
LOW
HI/Vcc
LOW
ON
OFF
OFF
ON
LOW
Vpp
Another prior art high voltage switch circuit is shown in
FIG. 2
(Prior Art). This circuit is designed to handle grounded gate problems via a cascode arrangement of MOSFET transistors. Cascoded N
3
and N
4
are connected at their respective gates to Vcc. The respective drain electrodes at N
1
and N
2
never reach Vpp but when the signal OUT node or the signal OUTB node is raised to Vpp, the drain electrodes are only at Vcc−Vtn, where Vt is the threshold voltage for the n-type MOSFETS, thus, the drain-source voltage, Vds, remains smaller than Vpp. Thus grounded gate breakdown is no longer a problem. Obviously, however, even more chip real estate is required than for the circuit of FIG.
1
. For the p-channel devices, cascoded P
3
and P
4
are tied to a gate bias voltage, GBIAS. That bias voltage is strategically selected according to design parameters to prevent grounded gate breakdown in the pull-up side of the circuit. However, to switch the switch, a timing sequence must be implemented, thus complicating design. In other words, initially to decode the correct En signal transition, GBIAS is held at zero volts until an En transition when signal OUTB is HIGH, then raise Vpp and GBIAS levels. Note also that the n-wells of the p-type devices P
1
-
4
are again tied to Vpp, but P
3
and P
4
are not source-tied to Vpp; therefore, separate n-wells are required, again adding design and fabrication complexity. Note also, the series-coupled extra transistors on both sides of the switch will be an inherently slower reacting circuit. Also this design still requires N-to-P size ratios because each N-stack must overcome the respective P-stack connected in series thereto to flip the switch between HIGH/LOW states. Thus, design and area complexity is a main drawback to this solution to the problems with high voltage CMOS switch circuits.
There is a need for a faster, small, simpler design for a high voltage CMOS switch.
SUMMARY OF THE INVENTION
In its basic aspects, the present invention provides a high voltage CMOS switch including: first devices for signal switching coupled to an input electrode, having a first logic state and a second logic state, and arranged as a parallel-connected, cascode input device and biased at a first electrical potential; and second devices for signal switching, coupled to said first devices and to a second electrical potential greater than said first electrical potential and to an output electrode, and arranged as a parallel-connected cascode output device coupled to said input electrode such that said second devices is pre-biased to said first electrical potential such that switching occurs at the output from said first electrical potential to said second electrical potential without said first devices being required to over-drive said second devices.
In another aspect, the present invention provides a high voltage switch circuit device, including: an input node; a first output node; a second output node; a first source of electrical potential level; a secon

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