High voltage CMOS signal driver with minimum power dissipation

Details High voltage CMOS signal driver with minimum power dissipation High voltage CMOS signal driver with minimum power dissipation

2000-03-30

2002-05-14

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S083000, C326S068000, C326S057000

Reexamination Certificate

active

06388470

ABSTRACT:

The present invention relates to the field of integrated circuit design and semiconductor chip fabrication. More particularly, the present invention relates to a voltage sensitive thin gate oxide complementary symmetry metal-oxide semiconductor (CMOS) fabricated circuit for transmitting high voltage signals.
BACKGROUND OF THE INVENTION
Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, electronic systems designed to provide these results attempt to include integrated circuit technology and transmit relatively high voltage signals.
Typically integrated circuits comprise a large quantity of electrical components or devices on a single small semiconductor chip. An important advantage of integrated circuits is their compact size. Utilizing modern integrated circuit fabrication techniques, the size of individual electrical devices (e.g., transistors) is constantly being reduced. However, as the size of the devices is reduced the devices become more sensitive. The materials used to form electrical devices in an integrated circuit have intrinsic characteristics that limit their performance capabilities such as conductivity capacity and ability to withstand electric field stresses. The ability of a component comprising a particular material to perform certain electrical functions is significantly impacted by the quantity of material included in the device. For example, as the three dimensional size of the device as a whole is scaled down, thinner gate oxide thickness on a CMOS device is required to maintain active performance levels. However, excessive electric field stresses have particularly detrimental affects on gates formed with relatively thin oxide layers.
FIG. 1
is an illustration of a P-type output CMOS device
100
exposed to high voltage electric field stress conditions while in an on state. P-type CMOS device
100
includes gate
110
, drain
120
, source
130
, substrate
140
and conduction channel
150
. Drain
120
and source
130
include positively doped material. Bulk
160
and substrate
140
include negatively doped material. Gate
110
is at a potential of zero volts. Drain
120
, source
130
and bulk
160
are at relatively high voltage potentials of Vhv. The differential voltage potential from gate
100
to drain
120
and source
130
cause electric field stresses on oxide layers forming gate
110
. For example as the voltage Vhv potential of drain
120
and source
130
increases relative to the 0V potential of gate
110
, the resulting electric fields cause the oxide layers forming gate
110
to deteriorate. This degradation has adverse impacts on the operations and longevity of the device.
Typically integrated circuits include input/output (I/O) buffer components that control input and output transmissions of electrical signals to exterior devices. Some applications require output electrical signals to be transmitted at relatively high voltages. The ability of a device to operate properly and with reasonable longevity while transmitting relatively high voltage electrical signals is largely determined by tolerances defined by the type of material included in the device and the thickness of the material. In some situations devices with thick gate oxide layers are capable of transmitting relatively high voltage signals but do not offer the cost advantages of relatively thin gate oxide devices. However, utilizing thin gate oxide devices to transmit relatively high voltage signals often results in electric fields that apply detrimental stresses to the device, and these detrimental stresses usually impede the performance and longevity of the device.
What is required is an integrated circuit system and method that includes relatively thin gate oxide devices capable of transmitting electrical signals at relatively high voltage levels without an excessively detrimental electric field build up across oxide layers forming a gate in the device. The thin gate oxide devices should operate without exacerbated longevity degradation due to excessive electrical field stresses across thin oxide gate layers. It should require no additional power supplies and should not cause the thin gate oxide device to dissipate addition al power in a static (non-switching) state.
SUMMARY OF THE INVENTION
The present invention is an integrated circuit system and method that includes relatively thin gate oxide CMOS devices capable of transmitting electrical signals at relatively high voltage levels without an excessively detrimental electric field build up across oxide layers forming a gate in the device. The system and method of the present invention facilitates the operations of thin gate oxide devices without exacerbated longevity degradation due to excessive electrical field stresses across thin oxide gate layers. The present invention does not require additional power supplies or reference voltages and does not dissipate additional power in a static (non-switching) state.
In one embodiment of the present invention, a degradation repression bias voltage component applies a degradation repression bias voltage signal to a gate of a high voltage output thin oxide gate CMOS device. The degradation repression bias voltage is set within a range that maintains a voltage differential from the gate of the output CMOS device to the source and the drain of the -output CMOS device such that the voltage differential does not cause excessive electrical field stresses on the gate. For example, in one embodiment of the present invention, a degradation repression bias voltage component utilizes a bias voltage range limiter to confine the voltage of a CMOS gate signal within an acceptable range. While a signal is propagating through the circuit a degradation repression bias voltage driver is utilized to actively drive and tightly hold the degradation repression bias voltage signal. After the signal has propagated through the circuit, the degradation repression bias voltage driver is de-activated.


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