Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1989-05-24
1993-01-19
Larkins, William D.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257389, 257900, 257409, 257408, H01L 2792
Patent
active
051810905
ABSTRACT:
A semiconductor memory and method of manufacture which are particularly useful for a high breakdown voltage EEPROM wherein high breakdown voltage transistors which are employed in a relatively large number and therefore greatly affect the integration density are formed with the masked offset structure, which is advantageous from the viewpoint of the integration density, while high breakdown voltage transistors which are not required in a large number and therefore have no large effect on the integration density are formed with the LOCOS offset structure, which requires a relatively small number of manufacturing steps and hence involves a relatively low production cost, and these two different types of transistors are fabricated on the same substrate. This arrangement enables optimization of the device structure in regard to miniaturization, reduction in the number or masks required and simplification of the manufacturing process.
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Ogura et al., "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field Effect Transistor", IEEE Trans. on Dev., pp. 1359-1367, Aug. 1980.
Larkins William D.
Seiko Epson Corporation
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