High voltage buffer for submicron CMOS

Details High voltage buffer for submicron CMOS High voltage buffer for submicron CMOS

1999-12-20

2002-03-26

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S068000, C326S083000

Reexamination Certificate

active

06362652

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to CMOS devices, and more particularly to a method and apparatus for allowing a submicron CMOS input buffer to receive an input signal having a voltage swing of 5V.
Conventionally 5V CMOS technologies have been used to fabricate analog and digital integrated circuits (ICs) that operate with a 5V supply voltage and input signals having a voltage swing of 5V. Advances in CMOS fabrication technologies allow fabrication of CMOS devices that are smaller in size than conventional 5V CMOS devices. The CMOS technologies for fabricating devices that are smaller in size than the conventional 5V CMOS devices are generally referred to as submicron CMOS technologies, and such devices are called submicron CMOS devices.
Submicron CMOS devices typically have an advantage of occupying a smaller area on an integrated circuit chip. This allows for increased logic density. Due to smaller sizes, the submicron CMOS devices generally use supply voltages that are lower than 5V. The submicron CMOS devices generally also require that input signals have a voltage swing of less than 5V.
Submicron CMOS devices with maximum allowable supply voltages of 3.3V and 2.5V have been fabricated. Providing an input signal having a high voltage swing, a maximum of which is higher than the maximum allowable supply voltage, to a submicron CMOS device, may result in a voltage breakdown (gate-oxide breakdown) of the submicron CMOS device. For example, CMOS devices fabricated using 0.25 &mgr; CMOS technology generally operate with a maximum allowable supply voltage of 3.3V, and have a gate-oxide breakdown voltage of 3.6V. Thus, if an input signal having a voltage swing of more than 3.6V is provided to a 0.25 &mgr; CMOS device, a voltage breakdown may occur.
Due to their smaller size and lower power consumption requirements, use of submicron CMOS devices typically results in smaller ICs and cost savings. However, voltage compatibility problems often arise because 5V CMOS devices are still being used concurrently. When 5V CMOS devices and submicron CMOS devices are used on the same board, more than one supply voltage having different voltage levels are generally needed. In addition, high voltage, e.g. 5V, swing signals generated by the 5V CMOS devices generally are not provided directly to the inputs of the submicron CMOS devices. This is due to the potential for voltage breakdown of the submicron CMOS devices upon receiving high voltage.
One method of providing supply voltages having different voltage levels is to use a separate voltage regulator to convert a 5V supply voltage to a supply voltage that is compatible with submicron CMOS devices. Such voltage regulators have been integrated into the submicron CMOS devices. The amount of area on the IC required to incorporate a voltage regulator is generally compensated by the increased density of IC chips fabricated using the submicron CMOS technologies. However, using voltage regulators is generally ineffective when the submicron CMOS devices are required to accept input signals having a high-voltage, e.g. 5V, swing.
One solution for reducing high-voltage swing at the input of the submicron CMOS devices is use of a resistor-based voltage divider. However, a resistor-based voltage divider has an associated power consumption and increases system loading. To decrease power consumption and loading effect, the size of the resistor generally needs to be large. Use of large resistors on integrated circuits is generally undesirable because large resistances occupy a large area of an IC chip.
SUMMARY OF THE INVENTION
The present invention is an input buffer fabricated using a submicron CMOS technology that is capable of receiving an input voltage swing of 5V.
One embodiment of the present invention is an integrated circuit comprising an input transistor and a bias transistor coupled to the input transistor. The input transistor receives an input signal having a voltage swing of a first range of voltages. The maximum of the first range of voltages is greater than or equal to a gate-oxide breakdown voltage of the input transistor. The bias transistor is a cascode transistor that controls internal voltage differences of the input transistor to be within a second range of voltages. The maximum of the second range of voltages is less than the gate-oxide break down voltage of the input transistor.
Another embodiment of the present invention is a buffer circuit comprising a charge down circuit, a charge up circuit and a current source circuit. The charge down circuit receives an input signal, generates a charge down signal to pull down an output of the buffer circuit to logic low. The charge up circuit receives the input signal, and generates a charge up signal to pull up the output of the buffer circuit to logic high. The current source circuit is coupled to the charge down circuit and the charge up circuit. The current source circuit includes a plurality of reference current sources, and provides reference currents to the charge down circuit and the charge up circuit.
Yet another embodiment of the present invention is a class-AB push-pull buffer circuit fabricated using submicron CMOS technologies.
Yet another embodiment of the present invention is a method of providing a high voltage input signal to an integrated circuit that includes the following steps: the high voltage input signal is provided at a gate of an input transistor; the input transistor is coupled to a bias transistor, which is a cascode transistor that controls voltage at a drain of the input transistor; and a selected bias voltage is provided to the bias transistor to control the voltage at the drain of the input transistor. The bias voltage is used to limit voltages within the input transistor to be less than a gate-oxide breakdown voltage for the input transistor.
Many of the attendant features of this invention will be more readily appreciated as the same becomes better understood by reference to the following detailed description considered in connection with the accompanying drawings.


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