Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Patent
1991-04-05
1993-11-30
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
365149, 365226, G11C 700
Patent
active
052672018
ABSTRACT:
A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating drift tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.
REFERENCES:
patent: 4433253 (1984-02-01), Zapisek
patent: 4697252 (1987-09-01), Furuyama
patent: 4740918 (1988-04-01), Okajima
patent: 4881201 (1989-11-01), Sato
Foss Richard C.
Gillingham Peter B.
Harland Robert F.
Lines Valerie L.
LaRoche Eugene R.
Mosaid Inc.
Zarabian A.
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