High-throughput memory-efficient BI-SOVA decoder architecture

Details High-throughput memory-efficient BI-SOVA decoder architecture High-throughput memory-efficient BI-SOVA decoder architecture

2011-04-12

2011-04-12

Abraham, Esaw T (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S792000, C714S794000, C714S796000, C375S262000, C375S265000, C375S341000

Reexamination Certificate

active

07925964

ABSTRACT:
Described herein are one or more implementations of a high-throughput and memory-efficient “windowed” bidirectional Soft Output Viterbi Algorithm (BI-SOVA) decoder. The described BI-SOVA decoder uses the “window” technique to concurrently decode several different non-overlapping portions of a subject signal in parallel.

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patent: 7200799 (2007-04-01), Wang et al.
patent: 7236546 (2007-06-01), Egnor et al.
patent: 7467347 (2008-12-01), Orio
patent: 7607072 (2009-10-01), Ashley et al.

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