High throughput FPGA control interface

Details High throughput FPGA control interface High throughput FPGA control interface

1995-12-11

1997-08-05

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 9, 326 39, H03K 19173

Patent

active

056546505

ABSTRACT:
A programmable logic device (PLD) including a plurality of programmable tiles organized in blocks. Each block comprises a unique subset of the plurality of programmable tiles. A data bus extends to each of the blocks. An independent address circuit is provided for each block. A block enable line is coupled to each block such that when the block enable is line is asserted the address circuit of a selected block is capable of transferring data from the data bus to the plurality of programmable tiles and when the block enable line is deasserted the data bus is substantially electrically isolated from the address circuit and data bus.

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patent: 4870302 (1989-09-01), Freeman
patent: 5336951 (1994-08-01), Josephson et al.
patent: 5394031 (1995-02-01), Britton et al.
patent: 5493239 (1996-02-01), Zlotnick

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