Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor
Reexamination Certificate
1998-02-26
2001-01-23
Kincaid, Kristine (Department: 2831)
Electricity: electrical systems and devices
Electrostatic capacitors
Fixed capacitor
C361S306100, C361S321100, C361S763000
Reexamination Certificate
active
06178082
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to multilayer electronic components and, in particular, to interposer thin film containing capacitors which use a noble metal such as platinum, iridium, palladium, ruthenium, silver, gold, etc. or alloys thereof as a capacitor electrode and to a diffusion barrier material (such as TaSiN, TiN, TaN, TiAlN, etc.) used in combination with the electrode to minimize circuitry oxidation and to provide an enhanced electronic component.
2. Description of Related Art
Multilayer substrates with capacitors have found wide spread use in electronics as integrated circuit packages. Electronic components are being made smaller in size with a higher circuit density and to meet these requirements it is necessary to use fabrication materials having enhanced properties such as increased conductivity, higher dielectric constant values, etc. Many of these materials however, do not have properties which enable their use with the other components of the multilayer substrate and accordingly, their use is limited in the fabrication of multilayer electronic components.
Ceramics have found widespread use in electronics as a substrate for integrated circuit packages including multilayer ceramic substrates having inner capacitors. In general, a metallized circuit pattern is applied to the ceramic substrate which is in the form of a greensheet, and the greensheet stacked with other metallized greensheets and the stack sintered to create a monolith of substrate and circuitry. Multilayer circuit packages are constructed by combining ceramic particles and organic binders into unfired or “greensheet” tape. Interlayer conductive pads, known as “vias”, are then inserted (punched) through the layer, and the vias filled with metals (Mo, Cu, W, etc.) forming electronic interconnections between the circuits. Metallized circuit patterns are then applied to the punched greensheet as is well known in the art and the layers stacked and sintered.
A capacitor can be formed within the multilayer substrate by sandwiching an inner dielectric layer between a pair of electrodes. Conductive pads are formed on the top sheet and wirings are formed within the substrate to connect the capacitor electrodes to the pads. U.S. Pat. Nos. 4,567,542; 5,065,275; 5,099,388 and 5,144,526 show such multilayer ceramic (MLC) products having internal capacitors and the disclosure of these patents are hereby incorporated by reference.
A capacitor structure can alternately be formed by using thin films of electrodes and dielectrics which are deposited on a prefabricated multilayer ceramic substrate. Typically, the bottom electrode is deposited using such techniques as sputter deposition, evaporation, chemical vapor deposition or sol-gel. The electrode is made from a noble metal (Pt, In, Ru, Pd, Ag—Pd, Au) or a noble metal oxide (IrO
2
, RuO
2
, etc.). The electrode may then be subjected to patterning by employing a photoresist stencil to define the pattern followed by wet or dry etching to delineate areas and thus create the pattern. This step is followed by deposition of the dielectric material using a physical or chemical vapor deposition method, or other techniques such as a spin-on technique. An example of films applied wet is a sol-gel film or other organic medium film which is heat treated leaving the inorganic dielectric component. The dielectric film may require one or more heat treatments in specific ambients such as oxidizing atmospheres to arrive at desired stoichiometries. An example of a dielectric film is barium titanate (BT), barium strontium titanate (BST) or barium zirconate titanate (BZT). These films can be deposited using a sputter deposition technique which employs an appropriate target in the presence of argon plasma, metallorganic chemical vapor deposition or sol-gel processing.
The dielectric film may then be patterned using a resist stencil and dry or wet etching methods. The final step is to put down the top electrode, which is typically selected from the above list of materials used for the bottom electrode, using methods such as those described above.
Platinum and other such desirable capacitor electrode materials are not an effective barrier in thin film components to the diffusion of oxygen in the temperature range used to fabricate the component. Oxygen moves readily through the platinum and oxidizes underlying vias and other circuitry wiring in the multilayer ceramic substrate which vias and circuitry may be made of Mo, Cu, W, etc. This oxidization results in either an electrical opening or a higher resistance path for the electrical signal, both of which are unacceptable.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a multilayer ceramic electronic component containing thereon a thin film postfire capacitor having a noble metal electrode such as platinum, iridium, palladium, ruthenium, silver, gold, etc. which component has enhanced electrical integrity and operating characteristics.
It is another object of the present invention to provide a method for forming an electronic component comprising a multilayer ceramic containing thereon a thin film postfire capacitor having a noble metal electrode which component has enhanced electrical integrity and operating characteristics.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one skilled in the art, are achieved in the present invention which is directed, in a first aspect, to an electronic component structure comprising:
a multilayer ceramic substrate comprising a plurality of ceramic layers having thereon metallized circuitry, interconnecting metallized vias and bottom to top vias;
a thin film structure electrically connected to the multilayer ceramic substrate, the thin film structure containing at least one capacitor comprising at least one lower first electrode comprising a layer of platinum or other noble metal and an upper second metal electrode with a dielectric material therebetween with each electrode layer being connected by wiring from the respective electrode to a corresponding pad on the surface of the thin film structure; and
a barrier layer of preferably TaSiN on the lower surface of the lower first electrode which barrier layer is between the platinum or other noble metal and the underlying metallized vias and circuitry.
In another aspect, the present invention relates to a method for fabricating an electronic component structure comprising:
forming a multilayer ceramic substrate by stacking layers of greensheets having metallization thereon and metal containing via interconnections and bottom to top vias and sintering the stack; and
forming a thin film structure on the surface of the multilayer ceramic substrate, the thin film structure containing at least one capacitor within said thin film structure comprising a first layer of platinum or other noble metal as a lower first electrode, a dielectric material layer formed on the surface of the platinum or other noble metal and an upper second layer of conductive metal on the surface of the dielectric as a second electrode, the first electrode and second electrode being connected to respective pads on the surface of the thin film structure by separate wirings from each electrode, the platinum (noble metal) first electrode having a barrier layer of preferably TaSiN deposited on the lower surface of the first electrode between the platinum (noble metal) and the underlying metal vias and metallized circuitry.
REFERENCES:
patent: 4349862 (1982-09-01), Bajorek et al.
patent: 4407007 (1983-09-01), Desai et al.
patent: 4567542 (1986-01-01), Shimada et al.
patent: 4954877 (1990-09-01), Nakanishi et al.
patent: 5043223 (1991-08-01), Kumagai et al.
patent: 5065275 (1991-11-01), Fujisaki et al.
patent: 5099388 (1992-03-01), Ogawa et al.
patent: 5144526 (1992-09-01), Vu et al.
pate
Farooq Mukta S.
Kotecki David E.
Rita Robert A.
Rossnagel Stephen M.
Ahsan Aziz M.
DeLio & Peterson LLC
International Business Machines - Corporation
Kincaid Kristine
Thomas Eric
LandOfFree
High temperature, conductive thin film diffusion barrier for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High temperature, conductive thin film diffusion barrier for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High temperature, conductive thin film diffusion barrier for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2517536