High-speed writable semiconductor memory device

Details High-speed writable semiconductor memory device High-speed writable semiconductor memory device

2006-12-12

2009-06-30

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S185240, C365S185270, C365S189011, C365S189110, C365S210120

Reexamination Certificate

active

07554862

ABSTRACT:
A memory cell array has a plurality of series connected memory cells connected to word lines and bit lines and arranged in a matrix. A select transistor selects from the word lines. A control circuit controls potentials of the word lines and bit lines in accordance with input data, and controls a data write operation, a data read operation, and a data erase operation executed on the memory cells. The select transistor is formed on a substrate. For a read operation, the substrate is supplied with a first negative voltage, a selected word line is supplied with a first voltage (first voltage≧first negative voltage), and unselected word lines are supplied with a second voltage.

REFERENCES:
patent: 6310374 (2001-10-01), Satoh et al.
patent: 6801458 (2004-10-01), Sakui et al.
patent: 7054195 (2006-05-01), Matsunaga
patent: 2004-192789 (2004-07-01), None

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