High-speed wide bandwidth data detection circuit

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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Details

C360S046000, C360S051000, C360S053000, C370S335000, C370S342000, C375S327000, C714S755000

Reexamination Certificate

active

10421512

ABSTRACT:
A high-speed, wide bandwidth data detection circuit includes a phase detection module, a data detection module, a loop filter, and a voltage controlled oscillator. The phase detection module is operably coupled to produce a controlled current based on a current mode mathematical manipulation of differences between an incoming data stream and a recovered clock. The phase detection module performs the current mode mathematical manipulations and produces the controlled current in the current domain. The data detection module is operably coupled to produce the detected data based on the incoming data stream and the recovered clock. The loop filter is operably coupled to convert the controlled current into a controlled voltage. The voltage controlled oscillator is operably coupled to convert the control voltage into the recovered clock.

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Jafar Savoj, Behzad Razavi; “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector”; IEEE 2001; IEEE Journal of Solid-State Circuits, vol. 36, No. 5; May 2001; pp. 761-767.

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