Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2006-02-21
2006-02-21
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S189040, C365S149000, C365S230050, C365S189050, C365S230080
Reexamination Certificate
active
07002868
ABSTRACT:
A semiconductor device has a memory cell array including a plurality of memory cells, each of which includes first and second transistors and connected in series between a bit line for normal access only and a bit line for refreshing only, and a capacitor connected to a connection node at which the first and second transistors are tied. A word line for normal access only and a word line for refreshing only are connected to control terminals of the first and second transistors, respectively. The semiconductor memory device has a late-write configuration in which writing to a memory cell at an externally input write address is performed, being delayed by a predetermined number of write cycles exceeding at least one, and has at least a circuit for checking whether the write address externally input the predetermined number of write cycles earlier matches the refresh address.
REFERENCES:
patent: 5856940 (1999-01-01), Rao
patent: 5963497 (1999-10-01), Holland
patent: 6233193 (2001-05-01), Holland et al.
patent: 6327210 (2001-12-01), Kuroda et al.
patent: 2004/0079968 (2004-04-01), Takahashi
patent: A-3-263685 (1991-11-01), None
patent: 2653689 (1997-05-01), None
patent: 9-190689 (1997-07-01), None
patent: 2001-143466 (2001-05-01), None
patent: P2001-283587 (2001-10-01), None
Sakurai et al., “Transparent-refresh DRAM (TReD) using dual-port DRAM cell,” Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, May 16-19, 1988, pp. 4.3/1-4.3/4.
Enhanced Memory Systems, Inc., Web Page Products News; Preliminary Datasheet, 72Mbit Pipelined BSRAM w/ NoBL Architecture 2M×36 (30 pages).
Hur J. H.
Muirhead and Saturnelli LLC
NEC Electronics Corporation
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