High speed transient active pull-up I 2 C

Details High speed transient active pull-up I 2 C High speed transient active pull-up I 2 C

2010-02-24

2010-12-28

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S087000, C710S105000, C710S305000

Reexamination Certificate

active

07859307

ABSTRACT:
An I2C-bus compatible device when functioning as a clock master comprises a transient active pull-up I2C (“TAP-I2C”) logic module having high side driver transistors, e.g., P-channel field effect transistors (FETs), coupled between a positive supply voltage and respective serial data (“SDA”) and serial clock (“SCL”) lines on the I2C bus. The high side output driver transistors for the SDA and SCL lines are sequentially pulsed on by the TAP I2C logic module for brief periods to first precharge the capacitance of the SDA line and then precharge the capacitance of the SCL line during low to high logic level transitions thereof. Precharging the capacitances of the I2C bus lines will also accelerate bus transfer operations for all I2C compatible devices since the capacitances of the I2C bus lines will be charged much faster through the low impedance active pull-up driver transistors then through the passive pull-up resistors.

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Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, (13 pages), Apr. 1, 2010.

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