High speed testing of semiconductor memory devices

Details High speed testing of semiconductor memory devices High speed testing of semiconductor memory devices

1984-08-14

1987-03-31

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

371 21, G11C 1140

Patent

active

046548270

ABSTRACT:
A semiconductor integrated circuit, such as a high-density, dynamic read/write memory containing an array of rows and columns of memory cells, is constructed to allow high speed testing to identify row line faults in one example, and to identify column or sense amplifier faults in another example. Row lines for the array in a dynamic RAM may contain detector circuits activated in a special test mode to produce a data output indicating integrity of each row line without requiring the access of the cells in the array in complex data patterns. The connection between bit lines in the array and sense amplifiers may be shifted or transposed in another embodiment to distinguish between column or sense amplifier faults; this construction also allows rapid loading of test patterns.

REFERENCES:
patent: 4055754 (1977-10-01), Chesley
patent: 4495603 (1985-01-01), Varshney
patent: 4541090 (1985-09-01), Shiragasawa
Rudy, "Memory Word Line Monitor", vol. 19, No. 2, Jul. 1976, p. 499.
Kelley, "Imbedded Memory Test Methods", vol. 21, No. 12, May 1979, pp. 4911-4913.

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