High speed testing of integrated circuit

Details High speed testing of integrated circuit High speed testing of integrated circuit

1984-08-02

1987-04-28

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

377 28, 371 21, G11C 700

Patent

active

046619305

ABSTRACT:
A register of the type used on as address counter in a dynamic RAM is tested by a method which does not require cycling through every possible value of the register contents. The counter is first loaded with a fixed value, all 1's or all 0's, and the contents checked by an AND or OR gate, producing a one-bit output which is monitored off-chip. Then, the carry feedback path to the counter register is altered, as by inverting all but the LSB, and the contents again checked, using the one-bit output via the AND or OR. In this manner, the operation of the counter is tested in three cycles.

REFERENCES:
patent: 4061908 (1977-12-01), de Jonge et al.

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