High speed test circuit for a semiconductor memory device

Details High speed test circuit for a semiconductor memory device High speed test circuit for a semiconductor memory device

1996-09-30

1999-07-27

Chung, Phung M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714718, G11C 2900

Patent

active

059283734

ABSTRACT:
A semiconductor memory device is tested by sequentially coupling a plurality of global input/output lines to a comparator which compares data bits from the global input/output lines sequentially rather than in parallel so as to reduce the number of output sense amplifiers. This reduces both the chip area, and the excessive current consumption caused by large numbers of sense amplifiers operating in parallel. The memory device includes a plurality of global input/output lines coupled to a memory cell array to receive data from the memory cell array. A global line select circuit generates sequential global line select signals during a test operation. A plurality of switch circuits selectively couples data from the global input/output lines to a sense amplifier responsive to the global line select signals. A comparator coupled to the output port of the sense amplifier sequentially compares a sequence of test data output from the sense amplifier and generates a result signal during the test operation.

REFERENCES:
patent: 5036494 (1991-07-01), Wise et al.
patent: 5060230 (1991-10-01), Arimoto et al.
patent: 5351213 (1994-09-01), Nakashima
patent: 5371708 (1994-12-01), Kobayashi
patent: 5450361 (1995-09-01), Iwahashi et al.
patent: 5694406 (1997-12-01), Liporski

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