High speed syndrome-based FEC encoder and decoder and system...

Details High speed syndrome-based FEC encoder and decoder and system... High speed syndrome-based FEC encoder and decoder and system...

2006-01-24

2006-01-24

Torres, Joseph D. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S782000, C714S784000

Reexamination Certificate

active

06990624

ABSTRACT:
A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.

REFERENCES:
patent: 5526368 (1996-06-01), Yun
patent: 5754563 (1998-05-01), White
patent: 6571368 (2003-05-01), Chen
Mastrovito, “VLSI Designs for Multiplication Over Finite FieldsGF(2m),” Int'l Conf. On Applied Algebra, Algebraic Algorithms, and Error-Correcting Codes, pp. 297-309, Rome (Jul. 1988).

Affiliated with

Also associated with

Rating

High speed syndrome-based FEC encoder and decoder and system... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed syndrome-based FEC encoder and decoder and system..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed syndrome-based FEC encoder and decoder and system... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3584307