High-speed synchronous memory device

Details High-speed synchronous memory device High-speed synchronous memory device

2006-04-04

2006-04-04

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S203000, C365S233100

Reexamination Certificate

active

07023746

ABSTRACT:
A synchronous semiconductor memory device has a read data bus for transferring data from a memory cell array to a read amplifier, and a write data bus for transferring data from a write driver to the memory cell array. To control equalization of the read and write data buses, an internal control clock signal is driven to a first level in delayed synchronization with an external clock signal, to a second level in synchronization with the external clock signal at the end of write operations, and to the second level in synchronization with a read amplifier control signal during read operations. The read and write data bus equalization times can therefore be separately optimized, enabling the memory to operate at a higher clock frequency than if the internal control clock signal were to be generated in the same way during both read and write operations.

REFERENCES:
patent: 6333895 (2001-12-01), Hamamoto et al.
patent: 6377512 (2002-04-01), Hamamoto et al.
patent: 6552959 (2003-04-01), Yamauchi et al.
patent: 2001-155485 (2001-06-01), None

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