Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1995-12-11
1998-09-01
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711167, 395881, 395880, G06F 938
Patent
active
058025960
ABSTRACT:
An SDRAM offering an increased operating speed and needing a limited area for layout is provided. In the synchronous DRAM, at least part of the signal processing to be executed continually is divided into a plurality of steps, the plurality of steps are executed concurrently in synchronization with an external clock applied externally, and thus the operating speed is increased. The synchronous DRAM comprises a plurality of pipes (i.e. plurality of pipeline stages) concurrently execute the plurality of steps, gates each of which is interposed between each pair of the plurality of pipes and controls passage of a signal between adjoining pipes, and gate control means each producing a pulsating control signal from an external clock and applying the control signal to a gate to control the gate in such a way that the gate will enter a transfer state immediately before an output from a pipe of a previous stage is finalized or enter a non-transfer state immediately after the output from the pipe of the previous stage is transferred to a pipe of the next stage.
REFERENCES:
patent: 5306962 (1994-04-01), Lamb
patent: 5426606 (1995-06-01), Takai
Fujitsu Limited
Peikari J.
Swann Tod R.
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