High speed static BiCMOS memory with dual read ports

Details High speed static BiCMOS memory with dual read ports High speed static BiCMOS memory with dual read ports

1989-12-20

1991-01-08

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

365203, G11C 1300

Patent

active

049842030

ABSTRACT:
A memory includes a plurality of cells with each cell containing a pair of cross-coupled N-channel field-effect transistors having set a reset nodes. Also in each cell, a first P-channel transistor couples a first select line to the set node; a first bipolar transistor couples the set node to a first bit line; a second P-channel trnasistor couples a second select line to the reset node; and a second bipolar transistor couples the reset node to a second bit line. Data is read from one port of the cell by pulling up just the set node via the first selected line and first P-channel transistor; and data is read from another port of the cell by pulling up just the reset node via the second select line and second P-channel transistor. Both such reads are fast since the parasitic capacitance of each select line is dependent on just a single pull-up transistor per cell. Also the cell is small in size since it is made with two less transistors than a conventional cell.

REFERENCES:
patent: 4858183 (1989-08-01), Scharrer

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