High-speed single-ended memory read circuit

Details High-speed single-ended memory read circuit High-speed single-ended memory read circuit

2007-12-06

2009-12-01

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Particular read circuit

C365S154000, C365S189060

Reexamination Certificate

active

07626871

ABSTRACT:
One embodiment of the present invention sets forth a high-speed single-ended memory read circuit that overcomes performance limitations of conventional single ended memory read circuits. A bit line keeper control mechanism for the high-speed single-ended memory read circuit is disclosed that automatically configures the bit line keeper for high-speed operation or low-speed operation, based on the frequency of a system clock. In high-speed operation, the bit line keeper is disabled, thereby eliminating short-circuit currents related to the bit line keeper and increasing the read performance of the single-ended memory read circuit. In low-speed operation, the bit line keeper is periodically disabled by a timer circuit to enable efficient read or write operations. Subsequent to the read or write operation, the bit line keeper is enabled to preserve state on the bit lines. By selectively enabling the bit line keeper, high-speed performance is improved while preserving correct function at low speeds.

REFERENCES:
patent: RE33694 (1991-09-01), McElroy
patent: 5646893 (1997-07-01), McMinn et al.
patent: 6014338 (2000-01-01), Wang et al.
patent: 6320795 (2001-11-01), Balamurugan et al.
patent: 7016239 (2006-03-01), Chatterjee et al.

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