High-speed sense amplifier of a semi-conductor memory device

Details High-speed sense amplifier of a semi-conductor memory device High-speed sense amplifier of a semi-conductor memory device

2000-06-15

2001-03-20

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S205000

Reexamination Certificate

active

06205072

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a high-speed sense amplifier of a semi-conductor memory device, more particularly to a high-speed sense amplifier of a semi-conductor memory device where a high-speed operation is possible both in the high voltage state that a power supply voltage is higher than a reference voltage and in the low voltage state that the power supply voltage is lower than the reference voltage by connecting a current mirror-type differential amplifier and an NMOS cross couple-type differential amplifier in parallel.
2. Description of the Related Art
Generally, a current mirror-type sense amplifier for amplifying the voltage being outputted according to a magnitude of an input voltage is comprised of a differential amplifier, the differential amplifier is comprised of a P-channel Metal Oxide Semi-conductor Transistor and an N-channel Metal Oxide Semi-conductor Transistor.
FIG. 1
shows a prior current mirror-type differential amplifier. The prior current mirror-type differential amplifier is comprised of a first and a second current mirror-type PMOS Transistor(P
1
, P
2
) of which sources are connected respectively to a power supply voltage(Vcc), a first and a second NMOS Transistor(N
1
, N
2
) of which drains are connected to drains of the first and the second PMOS Transistor(P
1
, P
2
) respectively.
A current of same amount flows in a drain of the first PMOS Transistor(P
1
) and a drain of the second PMOS Transistor(P
2
), so that a constant current flows in the first node(n
1
) connected to sources of the first and second NMOS Transistor(N
1
, N
2
).
And, An output voltage is determined by a difference between the voltages inputted to the gates of the first NMOS Transistor(N
1
) and the second NMOS Transistor(N
2
), at this time, an output voltage(Vout) is outputted in proportion to an input voltage(Vd) and an output resistance(rp
2
) of the second PMOS Transistor(P
2
) and an output resistance(rn
2
) of the second NMOS Transistor(N
2
).
FIG. 2
shows a prior current mirror-type sense amplifier which has a current mirror-type differential amplifier as a component. Referring to
FIG. 2
, the prior current mirror-type sense amplifier comprises a first amplifying part
100
for sensing and amplifying an inputting bit signal(b
1
b,
b
1
); an equalization means
30
for equalizing an output signal(sa
1
ob,
sa
1
o
) of the first amplifying part
300
when a first sense amplifier enable signal(pse
1
) is low; a second amplifying part
200
for sensing and amplifying a first amplifying signal(sa
1
ob,
sa
1
o
) sensed and amplified in the first amplifying part
100
; an output part
40
for outputting a second amplifying signal(sa
2
ob,
sa
2
o
) sensed and amplified in the second amplifying part
200
.
The first amplifying part
300
comprises a first current mirror-type sense amplifying part
10
and a second current mirror-type sense amplifying part
20
for sensing and amplifying a bit bar signal(b
1
b
) and a bit signal(b
1
). The first current mirror-type sense amplifying part
10
outputs an inverted signal(sa
1
ob
) among one pair of first amplifying signals(sa
1
ob,
sa
1
o
) by receiving the bit bar signal(b
1
b
) and the bit signal(b
1
), the second current mirror-type sense amplifying part
20
outputs a non-inverted signal(sa
1
o
) among the pair of first amplifying signals(sa
1
ob,
sa
1
o
) by receiving the bit bar signal(b
1
b
) and the bit signal(b
1
), a composition and an operation of the first and the second current mirror-type sense amplifying part
10
,
20
are same that of the current mirror-type differential amplifier indicated in FIG.
1
.
However, sources of NMOS Transistors(N
1
, N
2
) are coupled to a ground power supply in the first current mirror-type sense amplifying part
10
, sources of NMOS Transistors(N
4
, N
5
) are coupled to the ground power supply through a sixth NMOS Transistor(N
6
) in the second current mirror-type sense amplifying part
20
. Only in the case that the enable signal(pse
1
) of a first sense amplifier is inputted to gates of the third and the sixth NMOS Transistor(N
3
, N
6
), so that the enable signal(pse
1
) of the first sense amplifier is inputted in a high state, an operation of sensing and amplification is performed.
In the equalization means
30
, an output signal(sa
10
b
) of the first current mirror-type sense amplifying part
10
and an output signal(sa
1
o
) of the second current mirror-type sense amplifying part
20
are connected through a PMOS Transistor P
7
, the output signal(sa
10
b,
sa
1
o
) is inputted to PMOS Transistors P
5
, P
6
wherein a power supply is applied to a source, the enable signal(pse
1
) of first sense amplifier is inputted to gates of the fifth to seventh PMOS Transistors P
5
, P
6
, P
7
. When the enable signal(pse
1
) of the first sense amplifier is inputted in a high state, the fifth to seventh PMOS Transistors P
5
, P
6
, P
7
turn off, the first amplifying signal(sa
1
ob,
sa
1
o
) which is an output signal(sa
1
ob,
sa
1
o
) of the first and the second current mirror-type sense amplifying part
10
,
20
is normally inputted to the second amplifying part
200
. On the other hand, When the enable signal(pse
1
) of first sense amplifier is inputted in a low state, the second amplifying part
200
doesn't perform an operation of sensing and amplification by equalizing the first amplifying signal(sa
1
ob,
sa
1
o
) by way of turn on of the fifth to seventh PMOS Transistors P
5
, P
6
, P
7
.
The second amplifying part
200
is a part generating a second amplifying signal(sa
2
ob
) by receiving the signal(sa
1
ob,
sa
1
o
) sensed and amplified in the first amplifying part
300
, a composition and an operation of that is same that of the current mirror-type differential amplifier indicated in FIG.
1
. But, sources of NMOS Transistors N
7
, N
8
are connected to a ground power supply through an NMOS Transistor N
9
receiving a second sense amplifier enable signal(pse
2
) as an input signal of a gate. Accordingly, the second amplifying part
200
performs an operation of sensing and amplification only in the case that the second sense amplifier enable signal(pse
2
) is inputted in a high state.
An output part
40
is composed of a terminal outputting an output signal(sa
2
ob
) of the second amplifying part
200
as it is, an inverter IN
1
for inverting and outputting the output signal(sa
2
ob
).
If a sense amplifier enable signal(pse
1
) is inputted in a high state, PMOS Transistors P
5
, P
6
, P
7
of an equalizing means
30
turn off, the first amplifying part
100
outputs the signal(sa
1
ob,
sa
1
o
) that an input signal(b
1
b,
b
1
) is sensed and amplified. The second amplifying part
200
produces a second amplifying signal(sa
2
ob
) that the amplifying signal(sa
1
ob,
sa
1
o
) is sensed and amplified again, so that the output part
40
outputs the second amplifying signal(sa
2
ob
) and an inverted second amplifying signal(sa
2
o
).
However, a prior current mirror-type sense amplifier had a problem that if a power supply is inputted in a low voltage state which is lower than a reference voltage, an output signal of the current mirror-type sense amplifier doesn't follow well and an operation speed thereof is deteriorated.
SUMMARY OF THE INVENTION
This invention is invented to solve said problem, it is an object to provide a high-speed sense amplifier where a high-speed operation is possible both in the high voltage state that a power supply voltage is higher than a reference voltage and in the low voltage state that the power supply voltage is lower than the reference voltage by connecting a current mirror-type differential amplifier and an NMOS cross couple-type differential amplifier in parallel.
To accomplish said object of this invention, this invention is characterized to comprise, in a high-speed sense amplifier where a high-speed operation is possible both in the high voltage state that a power supply voltage is higher than a reference voltage and in the low voltage state that the power supply voltage

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