Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2002-11-04
2004-09-28
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S154000, C365S203000
Reexamination Certificate
active
06798704
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high speed SRAM, and particularly to a single ended SRAM with a high-speed sense amplifier and a data-hold circuit.
2. Description of the Related Art
Owing to the emergency of various video devices emerging, embedded SRAM has become indispensable portion. In order to make embedded SRAM read at high speed without affecting its internal data, a high speed sense amplifier with a data-hold circuit is necessary.
Most SRAM are implemented with differential sense amplifier, which has good common-mode-rejection-ratio. But, in a multiple process architecture, it is necessary to utilize multi-port memories. For the sake of saving chip space, single ended sense amplifiers are utilized in SRAM more frequently.
FIG. 1
shows a schematic diagram of a conventional single ended sense amplifier. When an input signal Vin is at low voltage level, a NMOS transistor N
10
is turned off. The NMOS transistor N
12
pulls up the voltage of a node A to some level at which a PMOS transistor P
16
and a NMOS transistor N
16
are both turned on such that the voltage of the node B is located between Vdd and Vss. Because the NMOS transistor N
12
forms a negative feedback, the voltage of the node A cannot be pulled up to Vdd. When the input signal Vin is at high voltage level, the NMOS transistor N
10
is turned on, discharging the node A such that the voltage of the node A decreases to a voltage level lower than the threshold voltage of the inverter
16
. Meanwhile, the NMOS transistor N
12
is turned on and the voltage of the node A is limited between the threshold voltage of the inverter
16
and Vss. When the input signal is at a high voltage level, the NMOS transistor N
12
and N
10
are both turned on, forming a DC conducting path in which the NMOS transistor N
12
impedes discharging the node A, therefore requiring more time to be pulled down to a low voltage level. There is a need for a novel sense amplifier incorporated in a SRAM, speeding up reading.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor memory and sense amplifier characterized by reading data at high speed and holding data.
To achieve the above objects, the present invention provides a semiconductor memory with a sense amplifier having an additional discharge path to speed up reading data. According to the embodiment of the invention, the semiconductor memory includes plural memory arrays having plural memory cells, a sense amplifier, and a latch circuit.
When a precharge signal is enabled, the plural memory cells are precharged. When the precharge signal is disabled, the sense amplifier's additional discharge path is enabled to speed up evaluation. The enabled precharge signal turns off a switch connected between the sense amplifier and the latch circuit to keep the latch from being affected by the sense amplifier during the precharge period.
REFERENCES:
patent: 6154403 (2000-11-01), Tanzawa et al.
patent: 6249479 (2001-06-01), Tanzawa et al.
patent: 489315 (2002-06-01), None
Chen Hsing-Yi
Lin Ming Chi
Birch & Stewart Kolasch & Birch, LLP
Nguyen Tan T.
Silicon Integrated Systems Corp.
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