Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2000-07-14
2001-10-30
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S210130
Reexamination Certificate
active
06310810
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains to a sense amplifier and to a method to operate the sense amplifier.
BACKGROUND OF THE INVENTION
Sense amplifiers are necessary for circuits that require the discrimination of signals into signals of different states, i.e., a defined logical state “1” or a logical state “0.” For example, these sense amplifiers are used in all integrated memory circuits for recognition of the digital state of a memory cell. Sense amplifiers can be used to determine the difference in the form of stored charges, cell currents or cell voltages.
In the article by Travis N. Blalock et al.: “A High-Speed Clamped Bit-Line Current-Mode Sense Amplifier,” IEEE Journal of Solid State Circuits, Vol. 28, No. 4, April 1991, p. 42ff, a related sense amplifier is described for a CMOS memory cell.
A sense amplifier of this kind compares an input signal, for example, the discharge capacitance of a memory cell, to a reference signal. The reference signal, whose value is between the two logical values, can be supplied by a so-called dummy memory cell, for example. The sense amplifier compares the two signals to each other. The line with the greater signal is released and a power supply voltage is applied to the signal to be amplified. If a logical “1” is to be allocated to the amplified data signal, then a positive power supply voltage is applied to the corresponding output line by means of a semiconductor circuit, for example. Conversely, a negative power supply voltage or a reference ground voltage is connected to the output line when the amplified data signal is to be a logical “0.”
Integrated semiconductor switches of this kind, which can be designed as MOSFETs for example, have a a typical threshold voltage of 0.7 V. Due to this threshold voltage, the particular power supply voltage will be applied to the data signal to be amplified with a time-delay. This so-called switching latency time corresponds to the time needed to drive the particular MOS semiconductor switch until it actually switches. Physically, the switching latency time represents the time needed for a MOSFET to form a channel. The switching latency time T
D
moves within a range of several ns to several &mgr;s depending on the driving current of the gate electrode of the MOSFET.
The capability of today's semiconductor memories depends in particular on the speed that data can be read from or written into the memory. In particular, this performance of the memory is also determined by the capability of the corresponding sense amplifier.
SUMMARY OF THE INVENTION
Proceeding from this state of the art, therefore, it is the objective of the present invention to disclose a sense amplifier that will allow a faster read-out of data from the memory cells of semiconductor memories.
An additional objective of the invention is to disclose a method for operation of the sense amplifier according to the invention.
The invention provides that the loading path output of the semiconductor circuit in the off state is precharged to a voltage that is just below the threshold voltage of the semiconductor switch. With a trigger signal that is to switch on the semiconductor switch, this switching process occurs nearly with no switching latency time, since the working point of the semiconductor switch is just slightly below its threshold voltage. Due to the precharging of the loading path output of the semiconductor switch according to the invention, the performance of the sense amplifier and thus of the entire semiconductor memory can be greatly increased for one read process.
The precharging of the loading path output of the semiconductor switch is done by means of a voltage generator. This voltage generator can be designed, for example, by a MOS transistor whose loading path is connected to a suitable reference voltage. Due to a corresponding triggering of the gate terminal of the MOS transistor, it can be switched to the loading path output of the semiconductor switch as necessary.
By precharging the loading path output of the semiconductor switch, it is possible to reduce the duration of a read cycle significantly. Alternatively or additionally, the sense amplifier according to this invention can sense and differentiate clearly smaller differential data signals during one read process. Based on these factors, a very high performance of the semiconductor memory is possible during read out due to a a-significant reduction in access times on the order of about 30%. Furthermore, this method allows clearly reduced power consumption. Finally, due to the reduction in the period of a read cycle and a smaller power consumption, an optimum signal-to-noise ratio can be obtained.
In a preferred configuration of the invention, a bit line decoder is provided for a semiconductor memory that has two complementary sense amplifiers for every two mutually complementary bit lines, these amplifiers are arranged precisely in-between these bit lines and one of them is used to amplify a first logic data level “1” and the other can be used to amplify a second logic data level “0.”
The sense amplifiers are each connected to the output of the bit lines via a transfer gate, and the outputs of these transfer gates are short-circuited to each other by means of a connecting line. This connecting line has a default voltage, typically the negative power supply voltage or the reference ground voltage. In particular, in very fast read processes, due to the parasitic capacities between the connecting line and the complementary bit lines, there will be undesirable noise.
As a solution, the invention provides a bit line decoder whose connecting line has a reference voltage, which typically corresponds to half the power supply voltage, applied to the output. By applying the reference voltage to the connecting line, the formation of parasitic capacitance between the connecting line and the bit lines can be mostly suppressed and thus the signal-to-noise ratio can be improved significantly.
REFERENCES:
patent: 4947376 (1990-08-01), Arimoto et al.
patent: 0211195 (1988-09-01), None
Betty Prince, “Semiconductor Memories”, 1983, 2nd Edition, pp. 221-222.
Nelms David
Tran M.
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