High-speed semicondustor memory integrated circuit arrangement h

Details High-speed semicondustor memory integrated circuit arrangement h High-speed semicondustor memory integrated circuit arrangement h

1991-05-06

1994-01-18

Mottola, Steven

Static information storage and retrieval

Read/write circuit

Plural use of terminal

36523003, G11C 1140

Patent

active

052804500

ABSTRACT:
A semiconductor integrated circuit is disclosed, in which a group of sense amplifiers activated at the same time by a selection signal on a selection signal line are divided into a plurality of blocks, and a power-source line for driving sense amplifiers is formed for each sense amplifier block so as to cross the selection signal line. Alternatively, an input/output line is divided into a plurality of sub-input/output lines, and a plurality of input/output lines are formed so that each input/output line crosses its sub-input/output lines, to form a hierarchical structure with respect to input/output lines. Thus, the load capacitance of each power-source line is reduced, and the time constant of each of the charging and discharging of the load capacitance is decreased. That is, the above semiconductor integrated circuit can operate at high speed.

REFERENCES:
patent: 4511997 (1985-04-01), Nozaki et al.
patent: 4811073 (1989-03-01), Kitamura et al.
Kumanoya et al., "A 90ns 1Mb DRAM with Multi-Bit Test Mode", 1985 IEEE Int'L S.S. Ckts Conference pp. 240-241.

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