High-speed semiconductor memory system

Details High-speed semiconductor memory system High-speed semiconductor memory system

1997-02-18

1997-12-30

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Signals

36523006, G11C 700

Patent

active

057038155

ABSTRACT:
A semiconductor memory system is provided in which a wave-pipeline operational frequency is enhanced by reducing the cycle time through a reduction in a difference in the signal delay time caused by differences of data path lengths. A delay circuit is inserted into a signal path having a smaller delay time between an address input section and data output section, thereby reducing a difference in the signal delay time caused by differences of data path lengths, which in turn reduces the cycle time to enhance the wave-pipeline operational frequency. Alternatively, an arrangement may be made to increase the signal delay time of a driver and/or sense amplifier for a smaller signal path length. In another aspect, a maximum differences in voltage drops between memory cells is reduced by controlling the resistance of a charge section for a bit line.

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K. Nakamura et al.; "A 220-MHz Pipelined 16-Mb BiCMOS SRAM with PLL Proportional Self-Timing Generator"; IEEE Journal of Solid-State Circuits, vol. 29, No. 11, Nov. 1994, pp. 1317-1322.
S. Kuhara et al.; "A 220MHz Pipelined 16Mb BiCMOS SRAM with PLL Proportional Self-Timing Generator"; Technical Report of IEICE, SDM94-32, ICD94-43 (1994-05) pp. 69-76.

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