High-speed semiconductor memory having internal refresh control

Details High-speed semiconductor memory having internal refresh control High-speed semiconductor memory having internal refresh control

2006-04-11

2006-04-11

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189070, C365S236000, C365S189020, C365S189120

Reexamination Certificate

active

07027344

ABSTRACT:
The refresh address generator of a memory includes, in part, a counter, a multitude of shift registers and multiplexers, and a comparator. With each clock cycle, the counter increments and stores the refresh count address, and the addresses stored in the counter and the shift registers prior to the increment operation is shifted out and stored in a pipelined fashion. If the array address stored in the last stage of the register pipeline is equal to the address of the array read out during the cycle immediately preceding the refresh cycle or is equal to the address of the neighboring array of the read out array, the comparator causes multiplexer to select the address stored in the counter as the refresh address. This address differs from the address of the array read out during the immediately preceding cycle by at least two counts.

REFERENCES:
patent: 6614698 (2003-09-01), Ryan et al.
patent: 2003/0169634 (2003-09-01), Kilmer et al.

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