Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-01-03
2003-03-25
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S207000, C365S230080
Reexamination Certificate
active
06538933
ABSTRACT:
This invention relates to a technology for improving an operation speed of a semiconductor memory device. More particularly, this invention relates to a technology that will be effective when used for semiconductor memory devices for which a high-speed operation is required, such as a clock synchronization type SRAM (Static Random Access Memory) and a dynamic RAM.
A memory access time and a cycle time are two important performance factors that determine high-speed performance of semiconductor memory devices such as SRAM (hereinafter called merely the “semiconductor memory” or the “memory”). The term “memory access time” means the time necessary for an address signal, a clock signal, etc, that are inputted from outside the memory to flow through a path for selecting the memory cell and to output desired data. The term “cycle time” means the time of the minimum cycle in which operations such as read and write operations can be executed normally.
FIG. 16
shows the construction of a synchronous SRAM the inventor of the present invention examined prior to the resent invention. An address input register
11
u
holds an address signal inputted from an address input buffer
22
u
at the timing at which a clock signal changes. A decoder
12
u
decodes this input address, and corresponding word line WL and bit lines BL, /BL are selected. Consequently, a memory cell MC connected to the selected word line and bit lines causes a read current to flow and generates a small potential difference in the selected bit lines. A sense amplifier
13
u
amplifies this relatively small potential difference and sends it as read data to an output register
14
u
. The data is sent from the output register
14
u
to an output buffer
15
u
at the timing at which the clock signal reaches the output register, and is outputted outside the memory chip.
Japanese Patent Laid-Cpen No. 4-28084 discloses a technology that establishes a test mode by elevating Vcc (power source voltage) at the time of a wafer test, decides the activation timing of the sense amplifier in such a fashion as to achieve the highest operation speed,on the basis of this test result, and sets permanently this timing by means of programmable elements such as fuses.
To utilize the technology described in this reference, however, the “test mode” must be established by elevating the power source voltage Vcc at the time of the test under the wafer state.
In other words, if semiconductor memory devices are assembled after they are confirmed to operate normally under the wafer state, they should certainly operate under such a wafer condition, but their operation is not always guaranteed under conditions other than the wafer condition. Therefore, the test under the wafer condition must be carried out under the condition where read-out of the data of the memory cell to the bit lines gets most retarded in comparison with the sense amplifier activation signal. When the read-out test is carried out under the condition where power source voltage dependence of the speed of the read data signal to the bit lines, that is determined by the memory cell current, and power source voltage dependence of the speed of a latch timing generation circuit of the sense amplifier are different (as is usually the case), for example, the semiconductor memory device is judged as operating normally at a certain power source voltage but is not judged as operating normally at another certain power source voltage. To avoid such a problem, the power source voltage must be freely set and controlled by external signals at the time of the test so that the read condition during the test under the wafer condition becomes the worst within the operation guarantee range.
The result of the examination made by the present inventor has revealed that it is not so easy to satisfy the condition, under which the memory cell read operation becomes the worst as described above, in the prior art example described in Japanese Patent Laid-Open No. 4-28084 because the potential of the power source voltage Vcc must be set to a high level beyond the normal operable range in the “test mode” under the wafer condition. After all, the sense amplifier activation timing must be set with a margin of a certain degree, and the highest memory access time the circuit can reach cannot be accomplished easily. Besides the prior art reference described above, mention can be made of Japanese Patent Laid-Open Nos. 7-21776 and 11-3593 that render adjustable the operation timing of the sense amplifier by the use of the set values of fuses and resisters.
These references do not describe the adjustment of the fall timing of the word line or the adjustment of the recovery operation time on the basis of the test result.
SUMMARY OF THE INVENTION
To reduce the memory cell access time and the cycle time in the semiconductor memory, it is effective to improve the operation speed of the sense amplifier for amplifying the read signal from the memory cell, for example. A latch type sense amplifier for amplifying a signal of a small amplitude by positive feedback is one of the high-speed sense amplifiers. To exploit fully high-speed performance of this latch type sense amplifier, it is extremely important to generate appropriately a latch activation signal.
FIG. 2
shows an example of the latch type sense amplification circuit the present inventor has examined. If the latch activation signal SALAT is too quick in this circuit, the latch activation signal is generated before the correct data is outputted from the memory cell. In other words, the previous data of the selected memory cell is outputted erroneously. However, if the latch activation signal SALAT is retarded unnecessarily to avoid this erroneous operation, the delay time of the sense amplifier increases.
This problem results after all in the problem how to establish timing between the data read out from the memory cell and the latch activation signal of the sense amplifier. In the conventional semiconductor memories, efforts have been necessary for timing the latch activation signal with the optimal sense latch time determined by the read current of the selected memory cell by constituting the delay circuit by using the same circuit as the circuit, through which the memory cell selection signal passes, and generating the latch activation signal.
However, it is difficult to precisely establishing the timing between the read timing of the memory cell and the timing of the latch activation signal unless characteristics of devices such as MOS transistors are clarified at the time of design. If the actual characteristics of the device are different from the characteristics of the device assumed at the time of design, this difference creates the deviation between the optimal read timing of the memory cell and the latch activation timing. So long as the read path of the memory cell and the delay time path of latch activation cannot be constituted into exactly the same circuit, the times of these paths cannot be made equal to each other. It is therefore necessary to set the latch timing with a margin for the time that is anticipated design-wise, and the problem remains unsolved that the highest memory access time, that the circuit can originally reach, cannot be acquired.
The result of the experiments carried out by the present inventors has revealed that power source voltage dependence of the latch timing of the sense amplifier is greater than that of the data output timing of the memory cell. In other words, the lower the power source voltage, the smaller becomes the margin of the latching timing of the sense amplifier. It is therefore easier to insure the normal operation of the memories over the entire power source voltage range necessary for insuring the normal operation when the test under the wafer state is carried out while the power source voltage is set to a value below the lower limit value of the operation guarantee voltage.
According to the studies of the present inventors, the problems to be solved for improving the speed of the cycle time are as follows.
The fir
Akioka Takashi
Shinozaki Masao
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