High speed semiconductor memory device having a high gain sense

Details High speed semiconductor memory device having a high gain sense High speed semiconductor memory device having a high gain sense

1982-06-01

1985-04-02

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

For complementary information

365207, G11C 1134

Patent

active

045091471

ABSTRACT:
In a static type RAM, a sense amplifier includes first and second dissymmetric type differential amplifier circuits each of which has a pair of differential transistors and an active load circuit such as a current mirror circuit connected to the drains of the differential transistors. One of balanced signals delivered from a memory cell is supplied to the non-inverting input terminal of the first dissymmetric type differential amplifier circuit and the inverting input terminal of the second dissymmetric type differential amplifier circuit. The other of said balanced signals is applied to the remaining input terminals of the first and second dissymmetric type differential amplifier circuits. As a result, notwithstanding that balanced signals cannot be delivered from each dissymmetric type differential amplifier circuit, amplified balanced signals can be obtained. The operating speed of the RAM can be raised owing to the fact that the dissymmetric type differential amplifier circuit having an active load circuit exhibits a comparatively high gain and the fact that the signal amplification by the balanced circuit is permitted.

REFERENCES:
patent: 3879621 (1969-04-01), Cavaliere et al.
patent: 4125878 (1978-11-01), Watanabe
patent: 4136292 (1979-01-01), Suzuki et al.
patent: 4138740 (1979-02-01), Itoh
patent: 4375039 (1983-02-01), Yamauchi
patent: 4375619 (1983-03-01), Saari
B. J. Hosticka, "Dynamic Amplifiers in CMOS Technology", Electronic Letters, 12/6/79, vol. 15, No. 25, pp. 819-820.
Yasui et al., "High Speed Low Power CMOS Static Rams", Electronic Engineering, Mar. 1981, pp. 51-55.
Electronik, H. 8, 1980, pp. 30 and 32.

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