High speed semiconductor memory device having a high gain sense

Static information storage and retrieval – Read/write circuit – Differential sensing

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365190, 365207, 307530, G11C 11413

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active

RE0340600

ABSTRACT:
In a static type RAM, a sense amplifier includes first and second dissymmetric type differential amplifier circuits each of which has a pair of differential transistors and an active load circuit such as a current mirror circuit connected to the drains of the differential transistors. One of balanced signals delivered from a memory cell is supplied to the non-inverting input terminal of the first dissymmetric type differential amplifier circuit and the inverting input terminal of the second dissymmetric type differential amplifier circuit. The other of said balanced signals is applied to the remaining input terminals of the first and second dissymmetric type differential amplifier circuits. As a result, notwithstanding that balanced signals cannot be delivered from each dissymmetric type differential amplifier circuit, amplified balanced signals can be obtained. The operating speed of the RAM can be raised owing to the fact that the dissymmetric type differential amplifier circuit having an active load circuit exhibits a comparatively high gain and the fact that the signal amplification by the balanced circuit is permitted.

REFERENCES:
patent: 3879621 (1979-04-01), Cavaliere et al.
patent: 4125878 (1978-11-01), Watanabe
patent: 4136292 (1979-01-01), Suzuki et al.
patent: 4138740 (1979-02-01), Itoh
patent: 4375039 (1983-02-01), Yamauchi
patent: 4375619 (1983-03-01), Saari
Minato et al., "HI-CMOSII 4K Static RAM", IEEE ISSCC, Digest of Technical Papers, Feb. 18, 1981, pp. 14-15, 253.
O'Connell et al., "Two Static 4K Clocked and Non-clocked RAM Designs", IEEE Jour. of Solid State Circuits, vol. SC-12, No. 5, Oct. 1977, pp. 497-501.
Hosticka, "Dynamic Amplifiers in CMOS Technology", Electronic Letters, Dec. 6, 1979, vol. 15, No. 25, pp. 819-820.
Yasui et al., "High Speed Low Power CMOS Static RAMs", Electronic Engineering, Mar. 1981, pp. 51-55.
Electronik, H. 8, 1980, pp. 30 and 32.
Yasui et al., Nikkei Electronics, Mar. 7, 1980, p. 142.
Kawarada, "A Fast 7.5 ns Access 1K-Bit RAM For Cache Memory Systems," IEEE Jour. of Solid State Circuits, vol. SC-13, No. 5, Oct. 1978, pp. 656-660.
Minato et al., "A High-Speed Low-Power Hi-CMOS 4K Static RAM", IEEE Transactions on Electron Devices, vol. ED-26, No. 6, Jun. 1979, pp. 882-885.
Tietze et al., "Semiconductor Circuitry" (Halbleiter-Schaltungstechnik), Corrected Reprint to the 3rd Edition, Springer-Verlag, Berlin, 1976, pp. 50-51 and translation thereof.

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