Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
2000-11-07
2003-01-07
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Multiple port access
C365S154000, C365S195000, C370S376000
Reexamination Certificate
active
06504786
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to electronic switching devices, switch fabrics and elements used in network systems and in particular to high speed scalable, dynamically programmable Tera-Bit Routing platforms.
2. Description of the Related Art
Current networking equipment and related systems operate at various levels in the OSI 7 layer structure shown in
FIG. 1. A
typical network can be divided in to several sections as shown in FIG.
2
. The first section or “access network” is used primarily for traffic aggregation from individual users. The second section comprises the “routing core” of the network and is used primarily for routing and a level of aggregation. The routers that form this routing core are designated as edge and core routers. The edge routers reside closer to the access network while the core routers connect multiple edge routers and sit in a centralized location closer to the backbone or the transport network.
The topology shown in
FIG. 2
is by no means the only way to implement the network but is meant to establish a frame of reference for the terminology used throughout the remainder of this document. For example, the partitioning of the network into sections becomes redundant in a converged scalable network. The network topology is entirely determined by cost and design considerations including the density of the end users per square mile, the distance between the successive distribution points within the network and the limitations of the devices/elements (design parameters) within this network.
All the elements in the access portion of the network work together to provide interfaces to the data traversing the network, by encapsulating them into the lower layers on the protocol stack as shown in FIG.
1
. The CPE or consumer premises equipment provides the higher layer interfaces between the end user (Layers
7
through
5
) and the rest of the network (Layers
4
through
1
). The physical layer is the actual transmission medium or channel through which data is carried at the “line rate.” The line rate is a characteristic of the physical channel on which data rides, i.e. different channels have different material and physical characteristics that determine the rate of transmission of data on that channel. A “physical layer protocol” is used to transmit data between any two nodes in network on the physical layer. Examples of this are found in the optical networking area, SONET (which uses packets/frames), DWDM (this exploits the channel characteristics of an optical fiber to create multiple bit pipes within the fiber).
Layer
2
, which is known as the data layer, carries data formatted to conform to given protocol or formats, which usually follow an open standard. For example, in a packet network, the information contained in the packets at each layer is the encapsulation or conversion (in cases where compression is used, it can not be looked as straight forward encapsulation), of the layer above it. A new header is added to each new packet that is formed from a data packet of the previous layer. This process is continued on down the stack till one reaches the actual physical layer and the packet format is conducive to physical layer transmission.
The IP and ATM protocols are Layer Three or Layer Two protocols. Thus, to understand what each element in the network is sending between any two points, one has to be able to understand what protocol is being used at each layer. This in common terminology is called terminating a certain protocol or interface, although terminating a protocol/interface can be used interchangeably. The major difference being, an ATM or an IP “interface” is a standard while an ATM/IP “protocol” is only representative of the layer at which it is being used, and is a subset of the standard.
The challenge is to utilize the available line rate to its maximum extent. In other words, the data rate is usually higher in terms of bits per second (bps) and therefore, the raw bit stream must be squeezed into the available channel, which is limited by the line rate. As mentioned above, the line rate is limited by the characteristics of the physical channel that is being used. Additionally, the actual utilization of the line rate is usually limited by the physical interface electronics, including the transceivers, which interface the PHY layer interface with a network device. The transceivers may be purely electrical or electro-optical, depending on the type of channel being used. Another factor that limits the utilization of the line rate maximum capacity is the architecture of the switching systems (DSLAMs, Routers, Switches etc.) of the core network as shown in FIG.
2
.
The typical architectures of the larger switching elements and the routing elements within the network are similar to that of SMP machines (symmetric multi-processing machines). These typically consist of a system with many interface cards known as the line side interfaces and a smaller number of cards providing what is called a trunk side interface. The trunk side interface is usually of a size that is a multiple of the size of the single line side interface. All the control and the management of such a system is provided by a processing or a controller card that is typically a single board microcomputer that has been specially designed for the task. This microcomputer may have a custom processor at it's core or a standard off the shelf RISC or CISC processor. The interconnect means includes a switch matrix, and a back-plane that forms a uniform physical interface for each of the cards to tie into.
One means of increasing the bit rate through the network is to increase the throughput between each of the elements of the switching system. This can be done using novel back-plane designs, novel back-plane architectures, new switch architectures or by optimizing the utilization of the standard architectures and designs by increasing the speed and efficiency of each of the various elements. The last option is widely employed as the fundamental architecture of switches and the switching systems has not changed significantly over the last few years. Most of the changes have therefore been the result of the ability to integrate more and more functions onto singe ICs, which leads to denser switches at a lower cost and with higher speed. There also have been incremental technology improvements in the solid-state electronics producing faster transceivers and higher clock speed devices which have further aided this quest for higher bandwidth.
Several back-plane architectures have been proposed, as well as several shared memory architectures. The limitations of these inventions lie primarily in their use of lookup tables, which are limited in both size and speed. This causes problems in realizing the next generation of real-time multi-media services which feature various grades of packet traffic (CBR, VBR, UBR). This is particularly true in the case of higher-level protocols that take up more over-head in terms of translation and abstraction from the physical layer.
Another limitation of the traditional routing architectures is the limited number of data packets that can be pushed through the network at any given time. Traditional switching back-planes (active or passive) and shared memory architectures typically form a non-blocking crossbar. The throughput of these crossbar switches is generally a function of the number of input ports, the number of output ports and the clock speed of the devices or device forming the switch. The theoretical maximum capacity, or throughput, is seldom achieved in an operating environment or in a practical setting, usually due to the limitations of the controller of the switch matrix, as well as synchronization and timing delays. Moreover, systems built using prior art switching devices are generally more complex in terms of the hardware switching elements as well as control software and hardware. This disadvantageously leads to higher cost system with limited scalability.
In sum, wh
Auduong Gene N.
Murphy, Esq. James J.
Nelms David
Winstead Sechrest & Minick P.C.
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