Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1987-09-22
1989-04-04
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Data refresh
365207, G11C 700
Patent
active
048192074
ABSTRACT:
A divided-bit line type dynamic random-access memory is disclosed which has parallel main bit line pairs in each of which sub-bit line pairs are provided to be electrically parallel with each other. Parallel word lines are provided on the substrate to insulatively cross the sub-bit line pairs. Memory cells are connected to crossing points of the sub-bit line pairs and the word lines. Main sense amplifiers are respectively connected to the main bit line pairs, sub-sense amplifiers are respectively connected to the sub-bit line pairs. A specific refreshing technique is utilized, according to which, when a refreshing operation is executed in a refreshing mode of the memory, the same number of word lines as that of sub-bit line pairs provided in each main-bit line pair are simultaneously selected, and the sub-sense amplifiers are activated to refresh together the memory cells which are connected to the work lines thus selected.
REFERENCES:
patent: 4367540 (1983-01-01), Shimohigashi
Sakui Koji
Watanabe Shigeyoshi
Kabushiki Kaisha Toshiba
Popek Joseph A.
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