High speed receive equalizer architecture

Details High speed receive equalizer architecture High speed receive equalizer architecture

2004-06-30

2009-11-24

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Receivers

Automatic gain control

C375S344000, C375S327000, C375S295000, C375S230000, C375S233000, C375S316000, C375S348000, C375S346000, C375S350000, C375S373000

Reexamination Certificate

active

07623600

ABSTRACT:
Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.

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