High speed RAID cache controller using accelerated graphics...

Details High speed RAID cache controller using accelerated graphics... High speed RAID cache controller using accelerated graphics...

1999-01-29

2001-06-19

Lefkowitz, Sumati (Department: 2781)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S120000, C711S114000

Reexamination Certificate

active

06249831

ABSTRACT:

BACKGROUND OF THE INVENTION
PCI stands for “peripheral component interface” defined by the PCI Special Interest Group in an effort to stem development of various local bus architectures. PCI bus communications include transactions between “master” and “slave” devices connected to the bus. The prior art is familiar with PCI bus architectures and master-slave communication protocols.
The prior art is also familiar with PCI bridge chips that connect together two PCI buses. These bridge chips can be used, for example, in transferring data from an initiating PCI bus to a target PCI bus. One prior art bridge chip is the DEC21154 chip from Intel, for example. These prior art bridge chips generally provide for sequential transfer of large bursts of data across the bridge.
FIG. 1
shows a prior art PCI bridge chip
10
connected between two PCI buses P
1
and P
2
in a dual PCI bus system
8
. As known in the art, host CPU
14
(e.g., a central processing computer board with a Pentium microprocessor) can connect to the PCI bus P
1
through its north-bridge chip set
14
a
, as shown. One exemplary chip set
14
a
, for example, is the Intel 440LX chip set. The PCI bridge chip
10
can also include a system accelerator
10
b
, and can connect to SDRAM
10
a
, used to store large burst data from the bridge
10
.
Various devices can also connect to the PCI buses P
1
, P
2
. By way of example, devices S
1
and S
2
connect, respectively, to PCI bus P
1
and P
2
and the chip set
14
a
can drive the devices S
1
and S
2
across the buses P
1
, P
2
. Devices S
1
, S
2
can for example be SCSI or Fibre Channel chips which interface to a storage bus
18
(typically either SCSI or Fibre Channel), as shown. Storage devices typically connect to SCSI buses
18
, as illustrated by SCSI device
16
connected to bus P
2
. SCSI device
16
interfaces to SCSI bus
18
which connects to disk drive
19
. In a typical example, the host CPU
14
issues a write command to the device
16
from primary PCI bus P
1
to secondary PCI bus P
2
through bridge chip
10
.
FIG. 1
also shows a south-bridge chip set
14
b
which connects to ISA bus
21
, as known in the art.
Standard PCI buses P
1
and P
2
provide a 32-bit, 33 MHz interface. Later generation chip sets
14
however support 66 MHz processing speeds. Faster bus speeds such as 66 MHz are thus desirable to support the newer chip sets
14
and to increase overall system processing power. However, higher bus speeds present problems in prior art systems such as system
8
: as the bus speed increases, the number of devices (e.g., devices S
1
, S
2
,
16
) connected to the buses P
1
, P
2
must decrease. For example, at 33 MHz, ten devices can connect to the buses P
1
, P
2
; yet only four devices can connect to the buses P
1
, P
2
at 66 MHz bus speeds. Accordingly, 66 MHz is not possible for buses P
1
and P
2
, as illustrated in
FIG. 1
, since there are too many devices connected to the buses.
This problem associated with increasing PCI bus speed affects a variety of PCI bus systems and controllers, including the RAID (Redundant Array of Inexpensive or Independent Disks) controller. A host server typically connects to the RAID controller via a SCSI (Small Computer System Interface) interface; and the bridge chip connects between dual PCI buses within the controller. One of the PCI buses provides connectivity to dual SCSI devices coupled to external disk drives functioning as the RAID storage. In that most RAID cache controllers of the prior art use the system PCI bus to handle data traffic, the bus is shared by many devices, reducing the rate of transfer between the host server CPU (central processing unit) and the RAID controller.
FIG. 1A
illustrates the problem further by showing one prior art RAID cache controller
20
. The controller
20
includes PCI interfaces
22
a
,
22
b
, which connect, respectively, to PCI buses
24
a
and
24
b
. Interfaces
22
route data onto appropriate internal buses
26
,
28
within the controller
20
according to PCI addressing. For example, interface
22
can route command data onto bus
26
and into PCI bridge
30
(e.g., bridge chip
10
, FIG.
1
); while routing burst data onto bus
28
, through the system accelerator
32
and into SDRAM
20
a
, e.g., SDRAM
10
a
, FIG.
1
. The architecture of controller
20
illustrates the competition which occurs on the PCI bus between (a) communication from the host chip set, e.g., chip set
14
a
,
FIG. 1
, to the controller's accelerator
32
and RAM
20
a
and (
b
) inter-PCI bus communication between the chip set and the target PCI bus, e.g., bus
24
a
to bus
24
b
communication.
One object of the invention is thus to provide a high speed processor-independent interface between a host CPU and its RAID controller. Another object of the invention is to provide systems and methods for isolating the RAID controller's PCI buses from the CPU's chip set to operate at higher bus speeds, even if the chip set's PCI bus operates at a lower bus speed. Yet another object of the invention is to provide a RAID cache controller which eliminates the above-mentioned bus competition problems. These and other objects will become apparent in the description that follows.
SUMMARY OF THE INVENTION
Current PCI chip sets provide an accelerator graphics port (“AGP”), used with graphic controllers, that operates at a higher speed and bandwidth than the chip set's PCI bus. By way of example, current chip sets connect to PCI buses with a 32-bit, 33 MHz interface; yet often provide an AGP that provides a higher 66 MHz or 133 MHz path, which is 2-3 times greater than the PCI bandwidth.
In one aspect, the invention provides a RAID cache controller with an accelerated graphics interface to connect the controller to an accelerated graphics port of a host CPU chip set. A first PCI bus interface couples the controller to a first PCI bus; and a second PCI bus interface couples the controller to a second PCI bus. A RAM port connects the controller to external RAM, and a first internal bus connects the RAM port to the first and second PCI interfaces. A first PCI bridge connects the accelerated graphics interface to the first PCI bus interface; and a second PCI bridge connects the accelerated graphics port to the second PCI bus interface. An accelerator, coupled to the accelerated graphics interface, communicates with the chip set without competition on the first and second PCI buses.
In another aspect, a second internal bus couples the accelerator to the RAM port.
In still another aspect, a third internal bus couples the first PCI bridge interface between the accelerated graphics interface and the first PCI interface.
In another aspect, a fourth internal bus couples the second PCI bridge interface between the accelerated graphics interface and the second PCI interface.
The invention also provides for a high-speed, multi-device PCI bus communication system, including a host CPU and a chip set (with an accelerated graphics port) for connecting the host CPU to a first PCI bus. A VLSI device (e.g., a RAID cache controller) has two PCI interfaces for communicating with second and third PCI buses, and an accelerated graphics interface for communicating with the accelerated graphics port. A first PCI bridge communicates between the accelerated graphics interface and the first PCI interface; and a second PCI bridge communicates between the accelerated graphics interface and the second PCI interface.
In still another aspect, a bus connects the accelerated graphics interface to the accelerated graphics port. In yet another aspect, the VLSI device includes a RAM port for connecting the VLSI device to external RAM.
In other aspects, the invention includes at least one SCSI or FC device coupled to the second PCI bus. Preferably, three SCSI or FC devices couple to the second PCI bus. Similarly, in another aspect, the invention includes at least one SCSI or FC device coupled to the third PCI bus; and preferably three SCSI or FC devices couple to the third PCI bus.
The utility device of the inventi

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