Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling
Reexamination Certificate
2007-05-01
2007-05-01
An, Meng-Al T. (Department: 2195)
Electrical computers and digital processing systems: virtual mac
Task management or control
Process scheduling
C710S200000, C712S028000
Reexamination Certificate
active
10268729
ABSTRACT:
A multiprocessor data processing system includes a plurality of processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. A first processor executes a high speed instruction sequence including a load-type instruction to acquire a promotion bit field within the global promotion facility exclusive of at least a second processor. The request may be made visible to all processors coupled to the interconnect. In response to execution of the load-type instruction, a register of the first processor receives a register bit field indicating whether or not the promotion bit field was acquired by execution of the load-type instruction. While the first processor holds the promotion bit field exclusive of the second processor, the second processor is permitted to initiate a request on the interconnect. Advantageously, promotion bit fields are handled separately from data, and the communication of promotion bit fields does not entail the movement of data cache lines.
REFERENCES:
patent: 4825358 (1989-04-01), Letwin
patent: 5050072 (1991-09-01), Earnshaw et al.
patent: 5237694 (1993-08-01), Horne et al.
patent: 5317749 (1994-05-01), Dahlen
patent: 5347636 (1994-09-01), Ooi et al.
patent: 5408629 (1995-04-01), Tsuchiva et al.
patent: 5463755 (1995-10-01), Dumarot et al.
patent: 5555417 (1996-09-01), Odnert et al.
patent: 5619671 (1997-04-01), Bryant et al.
patent: 5812876 (1998-09-01), Welker et al.
patent: 5826084 (1998-10-01), Brooks et al.
patent: 5937185 (1999-08-01), Weir et al.
patent: 5983329 (1999-11-01), Thaler et al.
patent: 6442664 (2002-08-01), Maynard et al.
patent: 6480918 (2002-11-01), McKenney et al.
patent: 6557091 (2003-04-01), Houldsworth
patent: 6578033 (2003-06-01), Singhal et al.
patent: 6678797 (2004-01-01), Chauvel et al.
patent: 2002/0156962 (2002-10-01), Chopra et al.
patent: 2003/0041225 (2003-02-01), Mattina et al.
patent: 2003/0163642 (2003-08-01), Borkenhagen et al.
patent: 2003/0208647 (2003-11-01), Kumar et al.
Arimilli Ravi Kumar
Williams Derek Edward
An Meng-Al T.
Dillon & Yudell LLP
International Business Machines - Corporation
Salys Casimer K.
Truong Camquy
LandOfFree
High speed promotion mechanism suitable for lock acquisition... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High speed promotion mechanism suitable for lock acquisition..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed promotion mechanism suitable for lock acquisition... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3759289