High speed processor interconnect tracing compaction using...

Details High speed processor interconnect tracing compaction using... High speed processor interconnect tracing compaction using...

2006-05-02

2006-05-02

Beausoliel, Robert (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S043000

Reexamination Certificate

active

07039834

ABSTRACT:
In particular, a system and method for receiving high speed processor bus traces for study of computer system capacity and operation uses a small FIFO memory and skips unused bus cycles to avoid the requirement for memory speed to match the processor bus speed. A time stamp is obtained to match each processor word to a time of occurrence to facilitate study of the trace data. Triggers are established to capture only those processor words that appear on the bus and which are also of interest. The remaining words are compacted by removing parts of the words that are not of interest from those words that remain in the queue based on the trigger criteria.

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