High speed phase locked loop test method and means

Details High speed phase locked loop test method and means High speed phase locked loop test method and means

1996-02-05

1998-07-14

Cunningham, Terry

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By pulse coincidence

327 20, 327 22, 327 27, 327159, 331DIG2, H03K 522

Patent

active

057810389

ABSTRACT:
A means and method for testing high speed phase locked loops (13) in an integrated circuit (12) at a test frequency lower than the operation speed of the phase locked loop (13). A test circuit portion (10) repeatedly tests for a zero level (42) of a recover clock signal (34) from the phase locked loop (13) and a latching flip flop (26) is set to provide a lock indication output (30) as long as repeated samples, taken at a test time (38) continue to indicate a zero level (42) of the recover clock signal (34). The test time (38) is the leading edge (40) of a reference clock signal (36) provided from an external source at a reference clock input (28) to the integrated circuit (12).

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