High speed phase alignment process and device

Details High speed phase alignment process and device High speed phase alignment process and device

2000-12-11

2003-04-15

Pham, Chi (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S376000

Reexamination Certificate

active

06549597

ABSTRACT:

This application is related to French Patent Application Number 9814991, filed Nov. 27, 1998.
TECHNICAL FIELD OF THE INVENTION
The present invention relates to phase alignment devices and relates more particularly to high speed phase alignment devices intended for alignment of data and clock signals.
BACKGROUND OF THE INVENTION
In a typical phase alignment device for recovering a serial data stream, a clock generator forms a multiphase clock signal. The alignment device determines which clock phase is nearest to the center of data bits within the stream of data, and then selects this clock phase for sampling the data stream.
SUMMARY OF THE INVENTION
The solution according to the invention differs from known solutions in that the algorithm used does not attempt to find the best phase for sampling the data, but rather tries to find the best position for a window of n bits in order to observe the flow of data, which is digitized with a precision of 1
of the clock period.
Inside of this observation window, the algorithm tries to find a transition front. When a transition front is found, the next bit is the data. This makes it possible to have a data length of T
, T being the clock period.
The invention relates to a process for alignment of phase between a data signal and a main clock signal, characterized by the fact that the flow of data of the input signal is divided into elements with a length equal to a fraction of the clock period by sampling of said input signal using signals taken from said clock signal which are phase-shifted with respect to one another by said fraction of a period of the main clock signal, the bits of data thus obtained are observed through a window with a length of a bit of the data signal, the window is moved so that the transition edges of the data bits are in its center, and the flow of data thus observed is transmitted to pipelines in which they under parallel processing, ensuring the extraction of the data bits which they contains.
According to a particular characteristic, the presence of a data bit in said sampled signal is determined either by the presence of a transition front or, in the absence of a transition front, by the last bit of the word.
Another aspect of the invention pertains to re-timing data to the most appropriate clock and to delivering the data with a reference clock in spite instabilities and distortion in the input data and in the clock signals.
The invention also relates to a phase alignment device for implementation of the process defined above, characterized by the fact that it includes some means of generation, from a main clock signal, of clock signals which are phase-shifted with respect to one another by a fraction of a period of said main clock signal, a drift compensation unit which uses as input the data coming from the pipelines and provides data in parallel form as output, said drift compensation being ensured by the intermediary of an output window, a first shift register for checking the position of the observation window, a second shift register for checking the position of the output window, a third shift register for checking the loading and unloading of the pipelines, and a control unit which manages the movement of the observation and output windows as a function of the information collected on the position of the transitions in the pipelines and as a function of the position of the observation window.
An advantage of the present solution is that a smaller length for the input data can be tolerated. Likewise, better immunity with regard to instabilities is ensured. Therefore, a higher operating frequency is allowed.


REFERENCES:
patent: 5550860 (1996-08-01), Georgiou et al.
patent: 5579352 (1996-11-01), Llewellyn
patent: 5692022 (1997-11-01), Haulin et al.
patent: 6285726 (2001-09-01), Gaudet
Texas Instruments Incorporated,Communication Channel, current pending patent application No. 09/368,055, filed Aug. 3, 1999.

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