High speed peripheral interconnect apparatus, method and system

Details High speed peripheral interconnect apparatus, method and system High speed peripheral interconnect apparatus, method and system

2006-08-29

2006-08-29

Cottingham, John R. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S306000, C710S311000

Reexamination Certificate

active

07099986

ABSTRACT:
A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect (“RegPCI”) bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP or a RegPCI device connected to the common AGP/RegPCI bus.

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