High speed peripheral interconnect apparatus, method and system

Details High speed peripheral interconnect apparatus, method and system High speed peripheral interconnect apparatus, method and system

2000-12-22

2003-04-29

Wong, Peter (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S107000, C710S105000

Reexamination Certificate

active

06557068

ABSTRACT:

TABLE OF CONTENTS
Background of the Invention
1. Field of the Invention
2. Description of the Related Technology
Summary of the Invention
Brief Description of the Drawings
Detailed Description of the Preferred Embodiments
I. Registered PCI Transaction Protocol
A. Overview of Registered PCI
B. Transaction Comparison Between Registered PCI and Conventional PCI
C. Registered PCI Transaction Protocol
1. Transaction Sequences
2. Allowable Disconnect Boundaries (ADB) and Buffer Size
3. Wait States
4. Addressing, Byte-Enables, and Alignment
5. Split Transactions
6. Bus Width
7. Source Sampling
8. Compatibility and System Initialization
D. Summary of Protocol Rules
1. Basic Initiator Rules
2. Basic Target Rules
3. Bus Arbitration Rules
4. Configuration Transaction Rules
5. Parity Error Rules
6. Bus Width Rules
E. Registered PCI Command Encoding
F. Registered PCI Extended Command Encoding
1. Validated Extended Command
2. Immediate Extended Command
G. Registered PCI Attributes
H. Byte-Count Transactions
1. Writes
2. Reads
I. Byte-Enable Transactions
1. Writes
2. Reads
J. Device Select Timing
1. Writes
2. Reads
K. Wait States
1. Writes
2. Reads
L. Configuration Transactions
M. Delayed Transactions
N. Split Transactions
1. Basic Split Transaction Requirements
2. Requirements for Accepting Split Completions
3. Split Completion Exception Message
4. Unexpected Split Completion Exceptions
O. Transaction Termination
1. Disconnect With Data
a. Initiator Termination and Disconnection
b. Target Disconnection
2. Target Retry Termination
a. Byte-Count Transactions
b. Byte-Enable Transactions
3. Split Response Termination
4. Master-Abort Termination
a. Byte-Count Transactions
b. Byte-Enable Transactions
5. Target-Abort Termination
a. Byte-Count Transactions
b. Byte-Enable Transactions
P. Bus Width
1. Data Transfer Width
2. Address Width
Q. Transaction Ordering and Deadlock-Avoidance
1. Ordering and Passing Rules
2. Required Acceptance Rules
R. Transaction Sequence Combining and Re-ordering
II. Arbitration
A. Arbitration Signaling Protocol
1. Starting a New Transaction
2. REQ# and GNT# Requirements
B. Arbitration Parking
III. Registered PCI Bridge Design Issues
A. Design Requirements for a Registered-PCI-to-Registered PCI Bridge
B. Design Requirements for a Registered-PCI-to-Conventional PCI Bridge
C. Bridge Error Handling
IV. Error Functions
A. Parity Generation
B. Parity Checking
C. Error Handling and Fault Tolerance
1. Data Parity Exception
2. Split Transaction Exceptions
V. Compatibility and System Initialization
A. Device Requirements
B. System Requirements
C. Frequency and Mode Initialization Sequence
1. Frequency and Mode Initialization Sequence in a Host Bridge
2. Frequency and Mode Initialization Sequence in a PCI-to-PCI Bridge
3. Hardware-Only Mode Switching Model
D. Interoperability Matrix
E. Hot Plug Events in a Registered PCI System
VI. Configuration Space
A. Registered PCI ID
B. Next Capabilities Pointer
C. Registered PCI Bridge Control
D. Registered PCI Command Register
E. Registered PCI Status Register
F. Memory Base Upper 32-Bits
G. Memory Base Limit Upper 32-Bits
VII. Electrical Specification
A. DC Specifications
B. AC Specifications
C. Maximum AC Ratings and Device Protection
D. Timing Specification
1. Clock Specifications
2. Timing Parameters
3. Measurement and Test Conditions
4. Device Internal Timing Examples
E. Clock Uncertainty
F. Reset
G. Pull-ups
H. Noise Budget
1. DC Noise Budget
2. Transient Noise Budget
I. System Timing
1. Timing Budget
J. Connector Pin Assignments
K. Power
1. Power Requirements
2. Sequencing
3. Decoupling
L. Expansion Board Trace Length and Signal Loading
M. Transmission Line Characteristics
VIII. Conventional PCI versus AGP 1.0 versus Registered PCI Protocol Rule Comparison
IX. Relaxed Ordering Rules
A. Background
B. System Topologies
1. Data and Trigger Near Writer
2. Data Near Writer, Trigger Near Reader
3. Data and Trigger Near Reader
4. Data Near Reader, Trigger Near Writer
C. I
2
O Usage Models
1. I
2
O Messaging Protocol Operation
2. Message Delivery with the Push Model
3. Message Delivery with the Pull Model
4. Message Delivery with the Outbound Option
5. Message Delivery with Peer to Peer
D. Rule Summary and Simplification
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer systems using a bus bridge(s) to interface a central processor(s), memory and computer peripherals together, and more particularly, in utilizing a registered peripheral component interconnect bus, logic circuits therefor and signal protocols thereof.
2. Description of the Related Technology
Use of computers, especially personal computers, in business and at home is becoming more and more pervasive because the computer has become an integral tool of most information workers who work in the fields of accounting, law, engineering, insurance, services, sales and the like. Rapid technological improvements in the field of computers have opened up many new applications heretofore unavailable or too expensive for the use of older technology mainframe computers. These personal computers may be used as stand-alone workstations (high end individual personal computers) or linked together in a network by a “network server” which is also a personal computer which may have a few additional features specific to its purpose in the network. The network server may be used to store massive amounts of data, and may facilitate interaction of the individual workstations connected to the network for electronic mail (“e-mail”), document databases, video teleconferencing, whiteboarding, integrated enterprise calendar, virtual engineering design and the like. Multiple network servers may also be interconnected by local area networks (“LAN”) and wide area networks (“WAN”).
Increasingly sophisticated microprocessors have revolutionized the role of the personal computer by enabling complex applications software to run at mainframe computer speeds. The latest microprocessors have brought the level of technical sophistication to personal computers that, just a few years ago, was available only in mainframe and mini-computer systems. Some representative examples of these new microprocessors are the “PENTIUM” and “PENTIUM PRO” (registered trademarks of Intel Corporation). Advanced microprocessors are also manufactured by Advanced Micro Devices, Digital Equipment Corporation, Cyrix, IBM and Motorola. These sophisticated microprocessors have, in turn, made possible running more complex application programs that require higher speed data transfer rates between the central processor(s), main system memory and the computer peripherals.
Personal computers today may be easily upgraded with new peripheral devices for added flexibility and enhanced performance. A major advance in the performance of personal computers (both workstation and network servers) has been the implementation of sophisticated peripheral devices such as video graphics adapters, local area network interfaces, SCSI bus adapters, full motion video, redundant error checking and correcting disk arrays, and the like. These sophisticated peripheral devices are capable of data transfer rates approaching the native speed of the computer system microprocessor central processing unit (“CPU”). The peripheral devices' data transfer speeds are achieved by connecting the peripheral devices to the microprocessor(s) and associated system random access memory through high speed expansion local buses. Most notably, a high speed expansion local bus standard has emerged that is microprocessor independent and has been embraced by a significant number of peripheral hardware manufacturers and software programmers. This high speed expansion bus standard is called the “Peripheral Component Interconnect” or “PCI.” A more complete definition of the PCI local bus may be found in the PCI Local Bus Specification, revision 2.1; PCI/PCI Bridge Specification, revision 1.0; the disclosures of which are hereby incorporated by reference. These PCI specifications are available from the PCI Special Interest Group, 2575 NE Kath

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