High speed parallel test architecture

Details High speed parallel test architecture High speed parallel test architecture

1994-01-13

1995-02-28

Mottola, Steven

Static information storage and retrieval

Read/write circuit

Testing

365220, 36518907, G11C 700

Patent

active

053943708

ABSTRACT:
The present invention is a dynamic type semiconductor memory device comprising a plurality of memory cells (not shown), plural pairs of bit lines, a first sense amplifier (20), arranged for each of the plural pairs of bit lines, for amplifying a bit line signal. A pair of data input/output lines extracts data from a pair of bit lines. A second sense amplifier (22), is arranged for each of said plural pairs of bit lines and consists of first and second driver MOS transistors (52 in FIG. 3) gates of which are connected to the pair of bit lines. The second sense amplifier is activated when said first sense amplifier is activated, for amplifying signals of the pair of data input/output lines. First and second column selecting transistors (30 in FIG. 2) are inserted between the pair of data input/output lines and the second sense amplifier and gates of which are connected to a column selecting line. A first write transistor (54 in FIG. 3) is connected between the first bit line and one output terminal of said second sense amplifier, the first write transistor being turned on in a data writing operation. A second write transistor (56 in FIG. 3) is connected between the second bit line and the other output terminal of the second sense amplifier, the second write transistor being turned on in a data writing operation.

REFERENCES:
patent: 4891792 (1990-01-01), Hanamura et al.
patent: 4914630 (1990-04-01), Fujishima et al.
patent: 5132937 (1992-07-01), Tuda et al.
patent: 5220527 (1993-06-01), Ohsawa
patent: 5305266 (1994-04-01), Rountree
Arimoto et al., "A 60-ns 3.3V-Only 16-Mbit DRAM w/Multipurpose Register", IEEE J. S. S. Ckts. v.24 n.5, Oct. 1989 pp. 1184-1190.
Kitsukawa et al., A 23-ns 1-Mb BiCMOS DRAM, IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1102-1111.

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