High speed parallel test architecture

Details High speed parallel test architecture High speed parallel test architecture

1991-03-22

1994-04-19

Mottola, Steven

Static information storage and retrieval

Read/write circuit

Testing

365220, G11C 700

Patent

active

053052668

ABSTRACT:
The present invention is a circuit comprising: a plurality of memory cells (not shown); a plurality of first amplifiers (each first amplifier is preferably comprised of; a plurality of sense amplifiers (e.g. 20), a block amplifier (e.g. 22), and a second means, preferably a block-I/O pair (e.g. 24 and 26), to connect the plurality of sense amplifiers to the block amplifier), wherein each first amplifier is selectively connected, preferably by a bitline pair (not shown), to a portion of the plurality of memory cells; a second amplifier (e.g. 34 in FIG. 2) connected to the plurality of first amplifiers by a first means, preferably a local-I/O pair (e.g. 28 and 32); and a means of comparing data, preferably determining whether the data are comprised of the same data states on the first means, from the selectively connected portions of the plurality of memory cells with data from the remainder of the selectively connected portions of the plurality of memory cells.

REFERENCES:
patent: 4891792 (1990-01-01), Hanamura et al.
patent: 4914630 (1990-04-01), Fujishima et al.
patent: 5132937 (1992-07-01), Tuda et al.
patent: 5134584 (1992-07-01), Boler et al.
"A 60-ns 3.3 V-Only 16-Mbit DRAM with Multipurpose Register", Arimoto et al., IEEE Journal of Solid State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1184-1190.

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