High speed parallel/serial link for data communication

Details High speed parallel/serial link for data communication High speed parallel/serial link for data communication

1999-06-11

2001-04-24

Nelms, David (Department: 2818)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S037000

Reexamination Certificate

active

06222380

ABSTRACT:

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS
The listed related patent applications are incorporated herein by reference:
Ser. No. 09/330,735, entitled: System that Compensates for Variances Due to Process and Temperature Changes;
Ser. No. 09/330,713, entitled: Initialization System for Recovering Bits and Group of Bits from a Communications Channel;
Ser. No. 09/330,743, entitled: Data Alignment Compensator;
Ser. No. 09/330,971, entitled: Low Power Differential Driver.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to communications network in general and, in particular, to systems for interconnecting electrical sub-systems such as modules, ASIC, etc.
2. Prior Art
The proliferation of computers and related electrical machines, such as routers, switches, servers, etc., have created a need for improved interconnection devices and methods. The need is present not only at the box level, but also at the sub-assembly level. The box level relates to interconnecting standalone boxes, such as workstations, personal computers, servers, routers, etc., whereas the sub-assembly level relates to components such as ASICS, modules, etc., within the boxes.
Traditionally two interconnecting approaches or techniques have been used. In one technique, a bus structure does the interconnection. Even though the bus structure transfers data relatively fast, it is expensive and requires multiple pins (one for each bit) at the interface. There are many designs in which pin counts and cost are very sensitive issues. As a consequence, bus structures are not suitable for interconnecting sub-assemblies.
In the other approach, serial links are used as the interconnecting mechanism. Even though the serial links solve some of the problems associated with the bus structures, they too have shortcomings which limit their use. Probably, the most severe of all the shortcomings is that the serial links are relatively low speed. For example, an RS232 serial link transmits data at approximately 115K bits/sec. Surely, this speed makes them unsuitable for use in high speed, say 500 and greater Mbps, applications.
The prior art has provided serial link devices with speed greater than RS232, albeit less than 500 Mbps. Even though these systems point in the right direction, they suffer several defects including unnecessary use of pins to transmit clock signal, etc.
Examples of the prior art systems are set forth in the following U.S. patents:
U.S. Pat. No. 5,081,654
U.S. Pat. No. 5,651,033
U.S. Pat. No. 5,533,072
U.S. Pat. No. 5,587,709
U.S. Pat. No. 5,675,584
U.S. Pat. No. 5,714,904
In view of the above, there is a need for a more efficient high speed interconnection system.
SUMMARY OF THE INVENTION
The interconnection system of the present invention is termed Data Aligned Serial Link (DASL) Interface. The DASL Interface receives data from a parallel interface such as a CMOS ASIC, partitions the bits from the parallel interface into a smaller number of parallel bit streams. The smaller number of parallel bit streams are then converted into a high speed serial stream, which is transported via a transmission medium to the receiver of the other module. A differential driver with control impedance drives the serial bit stream of data into the transmission media.
By simultaneously transmitting groups of bit streams serially over different transmission media, a high speed, high volume data path is provided. The data path uses fewer pins and transfers data at a faster rate than a traditional bus structure.
Prior to sending actual data, the system is initialized with a training procedure that sends a training pattern from the transmitter on one module to the receiver on the remote module. Preferably, the training pattern includes a 32-bit transmission rich sequence of 7 hex “A” patterns (1010) and 1 hex “5” pattern (0101). The purpose of the training pattern is to provide sufficient pattern edges so the receiver, through its algorithm, can acquire bit synchronization and then nibble synchronization to establish the most and least significant bits in the serial data stream when the bit stream is converted back into a 4-bit nibble.
The received data from each transmission medium is processed separately. The receiver converts the data into a single ended signal which is delayed over-sampled and latched. A controller examines the captured over-sampled data to determine wherein the series of latched positions data transition occur.
This is done to determine two sample points in the stream of oversampled data with the highest probability of uncorrupted data. The oversampled data which has the least probability of data error is the oversampled data contained in the latches farthest away from the data transitions. This is because all high speed systems have data jitter in the form of the system clock jitter, data intersymbol and transmission media distortions as well as system crosstalk that make the sample around data transitions uncertain as to data integrity. By averaging the positions determined to have transitioning data, the controller then determines which of the latched data to be used for the serial data samples. The sample points are selected by taking the locations of the data latches where data transitions occur, subtract the location numbers and add half the difference to the smaller location (done for two sequential data bits, giving two strobe positions). The controller acts as a digital software filter though this process by accumulating and averaging transition information and supplying the result of the accumulated data. This is important in that the best sample point is the point based upon the average points of transition, so as the sample does not respond to one piece of jitter, readjust its sample point and then sample the next bit in a location where the data integrity is uncertain. When actual data is sent in place of the training pattern, the sampled data will contain long run lengths where no transitions are present. When this occurs, no update in the algorithm sample point will occur.
The continuous updating by the controller algorithm also adjusts out temperature and initial technology process effects by basing the strobe point on the received data pattern strictly on the ongoing results of processed data input logic edges. As the transition edges move with temperature, so do the sample points. The controller can be time shared in applications having multiple high speed serial links, using only one controller functions for all links, to reduce cost.
Once the data stream has been adjusted for the best sample points, the two selected data streams are then fed into a series of latches and passed through two multiplexers (
FIG. 8
, MUX
46
, MUX
52
). Access of the output nibble is provided to the controller for adjusting the bits into their proper parallel order. The output nibble bit order is adjusted by the controller through manipulations of the control inputs to MUX
46
and MUX
52
.
To reconstruct the 4 bit nibble into its correct parallel order, an initial training pattern is suppled to the receiver, supplying a repeating pattern into the receiver with a unique end bit (7 “A's”, followed by a “5”). Adjustment of the bit order is performed by the controller which compares the serial string against a lookup template and through its various software states, adjust the nibble bit position.


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