Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2006-04-25
2006-04-25
Patel, Jay K. (Department: 2637)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S141000
Reexamination Certificate
active
07035368
ABSTRACT:
A digital system aligns a set of serial data receiver demultiplex circuits, thereby aligning the bits in the data words, while maintaining separate and optimally aligned data recovery clocks for each channel. The digital system generates a reference clock signal and one or more slave clock signals. Phase circuitry receives the slave clock signal and outputs a plurality of clock phase signals. A phase selection circuit receives the plurality of clock phase signals and selects an adjusted clock signal in response to a phase selection signal. A clock correlation circuit determines a phase difference between the reference clock signal and the adjusted clock signal and provides the phase selection signal to minimize the phase difference. The clock correlation circuit provides the phase selection signal from a counter.
REFERENCES:
patent: 5341405 (1994-08-01), Mallard, Jr.
patent: 5400370 (1995-03-01), Guo
patent: 5408473 (1995-04-01), Hutchison et al.
patent: 5425020 (1995-06-01), Gregg et al.
patent: 5488641 (1996-01-01), Ozkan
patent: 5777567 (1998-07-01), Murata et al.
patent: 5945855 (1999-08-01), Momtaz
patent: 6247138 (2001-06-01), Tamura et al.
patent: 6377644 (2002-04-01), Naudet
patent: 2002/0090045 (2002-07-01), Hendrickson
patent: 0 213 641 (1987-03-01), None
patent: 0 533 091 (1993-03-01), None
patent: WO 98/20655 (1998-05-01), None
Clock Distribution in Synchronous Systems; Eby G. Friedman J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering Online Copyright © 1999 by John Wiley & Sons, Inc. All rights reserved.
A 6 Gbps CMOS phase detecting DEMUX module using half-frequency clock; Nakamura, K., et al; VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on Jun. 11-13, 1998 Page(s):196-197.
SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application Greshishchev, Y.M.; Schvan, P.; Solid-State Circuits, IEEE Journal of vol. 35, Issue 9, Sep. 2000 Page(s):1353-1359.
Pickering Andrew J.
Simpson Susan M.
Surace Giuseppe
Brady III W. James
Marshall, Jr. Robert D.
Meek J.
Patel Jay K.
Telecky , Jr. Frederick J.
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