Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
Reexamination Certificate
1999-11-09
2002-08-20
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error count or rate
C714S712000
Reexamination Certificate
active
06438717
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the testing and control of the transmission of data which is conveyed, particularly from one network device to another over a link of substantial length, in synchronous serial data lines. The invention is particularly although not exclusively intended for use in systems where the data rate is very high, for example of the order of 800 megabits per second or higher.
BACKGROUND TO THE INVENTION
On example of a system to which the present invention is applicable is a system described in the earlier U.S. patent applications Ser. Nos. 09/196,215 and 09/196,216 filed Nov. 20, 1998, which describe a system in which a multiple bit parallel data signal has its individual bytes serialized and transmitted over a respective line of a set of synchronous serial data lines to a receiver at which the original signal is to be reconstituted. Such a system of transmission is suitable for communication between different chips in a network device composed of a multiplicity of chips.
One of the difficulties which arises in the operation of a system of this nature is that streams of data bits obtained by serialising parallel data bytes require proper byte alignment for the reconstitution of the data in its original form. In the aforementioned patent applications there is described a respective system in which the data lines are supplemented by an additional, control, line which may be used for phase alignment and other purposes. The applications describe various different methods, using both comparatively high frequency clocks and low frequency clocks for achieving mutual alignment of the various channels and the conveyance of ancillary or control data over the control line.
A variety of problems arise from the use of an otherwise beneficial system as described above.
In a system which operates at such high frequencies stand alone equipment required to test and obtain bit error rate figures is expensive and available to test only one channel at a time. Thus the true bit error rate must be calculated from an accumulation of data from each channel. Such a calculation is inherently inaccurate because it is not a true parallel test. Furthermore, the practical implementation of such testing is complex owing to the large number of external connections that would be required. Furthermore, known bit error rate testers, such as the Hewlett-Packard E4829B ATM Parallel Cell/Traffic Generator and Analyser or the Tektronix multiBERT MB 100 Bit Error Rate Tester have a maximum frequency of 100 MHz and require that device pins be made available for use as inputs and outputs. These are in addition to the connectors required for connection to the device under test.
Another operational problem with high speed links as described is that the failure of one channel, particularly the control channel, can cause the whole link to go out of service.
In a synchronous link as described, the bit error rate of each channel may be different, depending on, for example, how the printed circuit board tracking carrying the signals is routed. It would be desirable to ensure that the channel carrying control information be routed on the most robust line.
SUMMARY OF THE INVENTION
One aspect of the invention comprises the provision of on board bit error rate testing for a synchronous link, composed of a multiplicity of synchronized serial channels.
Another aspect of the invention is the employment of on board bit error rate testing to determine, for a multiplicity of serial data channels constituting a synchronous parallel bus, the bit error rates for each of the channel to reconfigure the link so that for example the channel which is designated as the control channel is changed to a different channel having a lower measured bit error rate.
In particular, when such a synchronized data link is first initialized, it may enter a mode which generates a bit error rate for each channel within the link. The control line may be assigned to the channel with the lowest bit error rate. If a pre-programmed error count threshold is exceeded during normal operation, the link may be forced into a set up mode wherein the control line is assigned to the channel with the lowest bit error rate and a multiplicity of channels (less than the actual number of channels) are allocated as data channels and the remaining channels with the highest bit error rates are excluded. Although such a scheme reduces the bandwidth of the link, the basic functionality of the link may be maintained.
Such a system increases robustness of the link by ensuring that control information is carried on the channel with a low bit error rate. It results in higher network availability through use of redundancy techniques, enables different configurations of the bus on different platforms and allows testing in the actual normal operational mode.
REFERENCES:
patent: 4059729 (1977-11-01), Eddy et al.
patent: 6289039 (2001-09-01), Garodnick
patent: WO 87/03717 (1987-06-01), None
Butler Joseph N
Fanning Neil O
Hughes Mark A
O'Neill Eugene
Quinlan Una
3Com Corporation
Nixon & Vanderhye PC
Tu Christine T.
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