High speed parallel binary multiplier

Details High speed parallel binary multiplier High speed parallel binary multiplier

1986-09-25

1989-02-28

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 752

Patent

active

048092118

ABSTRACT:
An n.times.n bit multiplier of a type having input and output registers and associated multiplexers, a multiplier array and adders, a shifter and an accumulator. The multiplier includes a temporary register having an input coupled in parallel with an input of the accumulator to an output of the shifter and an output coupled to a multiplexer for controlling the flow of output data from the temporary register to the multiplier array. The temporary register is responsive to a SELREG control signal to become enabled and disabled. An input of the shifter is coupled to an output of the adder.

REFERENCES:
patent: 4238833 (1980-12-01), Ghest et al.
patent: 4405992 (1983-09-01), Blau et al.
Blaauw et al., "Binary Multiplication", IBM Technical Disclosure Bulletin, vol. 4, No. 11, Apr. 1962, pp. 32-34.

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